Combine the following separate plain text based bindings to YAML:
lpc1850-creg-clk.txt
pc1850-dmamux.txt
phy-lpc18xx-usb-otg.txt
Additional changes:
- remove label in example.
- remove dmamux consumer in example.
- remove clock consumer in example.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
Link: https://lore.kernel.org/r/20250602143612.943516-1-Frank.Li@nxp.com
Signed-off-by: Lee Jones <lee@kernel.org>
Convert the TI DA830 USB PHY binding to DT schema format. Add "clocks"
and "clock-names" which are already in use. As they are always present,
make them required as well.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: David Lechner <david@lechnology.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250627220107.214162-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Examples should not have the 'status' property and 'okay' is anyway by
default.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250701063636.23872-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Document the Synopsys eUSB2 PHY on the Milos SoC by using the SM8550 as
fallback.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-eusb-phy-v3-2-6c3224085eb6@fairphone.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
On SM8750, the M31 eUSB2 PHY is being used to support USB2. Add the
binding definition for the PHY driver.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
Signed-off-by: Melody Olvera <melody.olvera@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250527-sm8750_usb_master-v6-2-d58de3b41d34@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Add an entry to the compatible field for SM8750 for the QMP combo PHY.
This handles the USB3 path for SM8750.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
Signed-off-by: Melody Olvera <melody.olvera@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250527-sm8750_usb_master-v6-1-d58de3b41d34@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Document support for the USB2.0 phy found on the Renesas RZ/V2N
(R9A09G056) SoC. The USB2.0 phy is functionally identical to that on the
RZ/V2H(P) SoC, so no driver changes are needed. The existing
`renesas,usb2-phy-r9a09g057` compatible will be used as a fallback
for the RZ/V2N SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20250528133858.168582-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Convert the Marvell Armada-375 USB and MVEBU SATA PHY binding to DT
schema format. It's a straight forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20250607212609.743346-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Convert the TI Keystone USB PHY binding to DT schema format. Drop the
"#address-cells" and "#size-cells" properties which don't make sense
without any child nodes.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250607212641.744683-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Convert the TI DM816x USB PHY binding to DT schema format. It's a
straight forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250607212634.744373-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
The Exynos7870 MIPI PHY device contains one DSIM PHY block and three
CSIS PHY blocks. It also requires two sysregs, one for display, and the
other for cameras. Document this device.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250612-exynos7870-mipi-phy-v1-1-3fff0b62d9d3@disroot.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Add a compatible for the exynos990-usbdrd-phy. The PHY is compatible with
the older exynos5420 design (two clocks) when running in highspeed mode.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
Link: https://lore.kernel.org/r/20250515-usb-resends-may-15-v3-1-ad33a85b6cee@mentallysanemainliners.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Add compatible for the USB2 phy in the Rockchip RK3562 SoC.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250415050005.52773-1-kever.yang@rock-chips.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Add compatible for the USB2 phy in the Rockchip RK3036 SoC.
Apart from some bits that got swapped around in the phy registers, the
block is nearly the same as the one on the rk3128.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250503201512.991277-2-heiko@sntech.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Document USB2.0 phy bindings for RZ/V2H(P) ("R9A09gG57") SoC.
RZ/V2H(P) USB2.0 phy is similar to one found on the RZ/G2L SoC, but it
needs additional configuration to be done as compared RZ/G2L USB2.0 phy.
To handle this difference a SoC specific compat string is added for
RZ/V2H(P) SoC.
Like the RZ/G2L SoC, the RZ/V2H(P) USB2.0 PHY requires the `resets`
property and has two clocks.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250414145729.343133-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
The RZ/G2L family requires two clocks for USB2 PHY, which are already
defined in the DTSI files. Add a constraint in the DT binding document
to ensure validation with `dtbs_check`.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250414145729.343133-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Document support for Exynos2200. As the USBDRD 3.2 4nm controller
consists of Synopsys eUSB2.0 phy and USBDP/SS combophy, which will
be handled by external drivers, define only the bus clocked used
by the link controller.
Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250504144527.1723980-3-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Document the exynos2200 eUSB2 compatible. Unlike the currently documented
Qualcomm SoCs, the driver doesn't make use of reset lines for reset
control and uses more clocks.
Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250504144527.1723980-2-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Convert the Rockchip RK3399 PCIe PHY to DT schema format. Move the
example to the GRF binding as that has the complete block.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250415011824.2320039-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
The parameter value of below 3 properties are USB PHY specific. i.MX8MP
and i.MX95 USB PHY has different meanings. This will enlarge parameters
value and add constraints for them.
- fsl,phy-tx-vref-tune-percent
- fsl,phy-tx-rise-tune-percent
- fsl,phy-comp-dis-tune-percent
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250430094502.2723983-2-xu.yang_2@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
The ticket TKT0676370 shows the description of TX_VBOOST_LVL is wrong in
register PHY_CTRL3 bit[31:29].
011: Corresponds to a launch amplitude of 1.12 V.
010: Corresponds to a launch amplitude of 1.04 V.
000: Corresponds to a launch amplitude of 0.88 V.
After updated:
011: Corresponds to a launch amplitude of 0.844 V.
100: Corresponds to a launch amplitude of 1.008 V.
101: Corresponds to a launch amplitude of 1.156 V.
This will correct it accordingly.
Fixes: b2e75563dc ("dt-bindings: phy: imx8mq-usb: add phy tuning properties")
Cc: stable@vger.kernel.org
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250430094502.2723983-1-xu.yang_2@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Add a compatible string for the MediaTek Dimensity 1200 (MT6893)
SoC: this chip integrates a MediaTek generic T-PHY version 2.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250416120220.147798-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Add support for the MediaTek Dimensity 1200 (MT6893) SoC: the DSI
PHY found in this chip is fully compatible with the one found in
the MT8183 SoC.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250416120220.147798-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Convert the Rockchip RK3399 Type-C PHY to DT schema format. Add the
missing "power-domains" property and "port" and "orientation-switch"
properties in the child nodes.
Omit the previously deprecated properties as they aren't used anywhere.
Drop the 2nd example which was pretty much identical to the 1st example.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250416202419.3836688-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
The Cadence Torrent SERDES supports USXGMII protocol. Hence, update the
bindings to allow PHY_TYPE_USXGMII. Since PHY_TYPE_USXGMII has the value
of "12" while the existing maximum allowed PHY TYPE is "9", switch back to
using "enum" property in the bindings to account for this discontinuity.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250411055743.623135-1-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Add support for type switch by pericfg register between USB3/PCIe.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250422132438.15735-5-linux@fw-web.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Add compatible for xs-phy on mt7988.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250422132438.15735-4-linux@fw-web.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>
