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https://git.proxmox.com/git/qemu
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8555f71dcb
Move more misc helpers from helper.c to misc_helper.c. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
125 lines
3.6 KiB
C
125 lines
3.6 KiB
C
/*
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* Miscellaneous PowerPC emulation helpers for QEMU.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "helper.h"
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#include "helper_regs.h"
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/*****************************************************************************/
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/* SPR accesses */
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void helper_load_dump_spr(CPUPPCState *env, uint32_t sprn)
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{
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qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn,
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env->spr[sprn]);
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}
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void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
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{
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qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn,
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env->spr[sprn]);
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}
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#if !defined(CONFIG_USER_ONLY)
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#if defined(TARGET_PPC64)
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void helper_store_asr(CPUPPCState *env, target_ulong val)
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{
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ppc_store_asr(env, val);
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}
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#endif
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void helper_store_sdr1(CPUPPCState *env, target_ulong val)
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{
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ppc_store_sdr1(env, val);
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}
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void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
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{
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target_ulong hid0;
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hid0 = env->spr[SPR_HID0];
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if ((val ^ hid0) & 0x00000008) {
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/* Change current endianness */
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env->hflags &= ~(1 << MSR_LE);
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env->hflags_nmsr &= ~(1 << MSR_LE);
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env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
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env->hflags |= env->hflags_nmsr;
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qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__,
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val & 0x8 ? 'l' : 'b', env->hflags);
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}
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env->spr[SPR_HID0] = (uint32_t)val;
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}
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void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
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{
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if (likely(env->pb[num] != value)) {
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env->pb[num] = value;
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/* Should be optimized */
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tlb_flush(env, 1);
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}
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}
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void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val)
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{
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store_40x_dbcr0(env, val);
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}
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void helper_store_40x_sler(CPUPPCState *env, target_ulong val)
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{
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store_40x_sler(env, val);
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}
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#endif
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/*****************************************************************************/
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/* PowerPC 601 specific instructions (POWER bridge) */
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target_ulong helper_clcs(CPUPPCState *env, uint32_t arg)
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{
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switch (arg) {
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case 0x0CUL:
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/* Instruction cache line size */
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return env->icache_line_size;
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break;
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case 0x0DUL:
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/* Data cache line size */
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return env->dcache_line_size;
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break;
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case 0x0EUL:
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/* Minimum cache line size */
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return (env->icache_line_size < env->dcache_line_size) ?
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env->icache_line_size : env->dcache_line_size;
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break;
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case 0x0FUL:
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/* Maximum cache line size */
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return (env->icache_line_size > env->dcache_line_size) ?
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env->icache_line_size : env->dcache_line_size;
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break;
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default:
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/* Undefined */
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return 0;
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break;
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}
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}
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/*****************************************************************************/
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/* Special registers manipulation */
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/* GDBstub can read and write MSR... */
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void ppc_store_msr(CPUPPCState *env, target_ulong value)
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{
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hreg_store_msr(env, value, 0);
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}
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