mirror of
https://git.proxmox.com/git/qemu
synced 2025-10-31 11:31:38 +00:00
111bfab3b5
This is needed by OS/2 and Windows NT and some programs like VirtualPC. This patch has been tested using OS/2 bootloader (thanks to Tero Kaarlela). (Jocelyn Mayer) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1379 c046a42c-6fe2-441c-8c8c-71466251a162
372 lines
9.5 KiB
C
372 lines
9.5 KiB
C
/* External helpers */
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void glue(do_lsw, MEMSUFFIX) (int dst);
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void glue(do_stsw, MEMSUFFIX) (int src);
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static inline uint16_t glue(ld16r, MEMSUFFIX) (target_ulong EA)
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{
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uint16_t tmp = glue(lduw, MEMSUFFIX)(EA);
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return ((tmp & 0xFF00) >> 8) | ((tmp & 0x00FF) << 8);
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}
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static inline int32_t glue(ld16rs, MEMSUFFIX) (target_ulong EA)
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{
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int16_t tmp = glue(lduw, MEMSUFFIX)(EA);
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return ((tmp & 0xFF00) >> 8) | ((tmp & 0x00FF) << 8);
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}
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static inline uint32_t glue(ld32r, MEMSUFFIX) (target_ulong EA)
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{
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uint32_t tmp = glue(ldl, MEMSUFFIX)(EA);
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return ((tmp & 0xFF000000) >> 24) | ((tmp & 0x00FF0000) >> 8) |
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((tmp & 0x0000FF00) << 8) | ((tmp & 0x000000FF) << 24);
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}
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static inline void glue(st16r, MEMSUFFIX) (target_ulong EA, uint16_t data)
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{
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uint16_t tmp = ((data & 0xFF00) >> 8) | ((data & 0x00FF) << 8);
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glue(stw, MEMSUFFIX)(EA, tmp);
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}
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static inline void glue(st32r, MEMSUFFIX) (target_ulong EA, uint32_t data)
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{
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uint32_t tmp = ((data & 0xFF000000) >> 24) | ((data & 0x00FF0000) >> 8) |
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((data & 0x0000FF00) << 8) | ((data & 0x000000FF) << 24);
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glue(stl, MEMSUFFIX)(EA, tmp);
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}
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/*** Integer load ***/
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#define PPC_LD_OP(name, op) \
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PPC_OP(glue(glue(l, name), MEMSUFFIX)) \
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{ \
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T1 = glue(op, MEMSUFFIX)(T0); \
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RETURN(); \
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}
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#define PPC_ST_OP(name, op) \
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PPC_OP(glue(glue(st, name), MEMSUFFIX)) \
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{ \
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glue(op, MEMSUFFIX)(T0, T1); \
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RETURN(); \
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}
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PPC_LD_OP(bz, ldub);
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PPC_LD_OP(ha, ldsw);
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PPC_LD_OP(hz, lduw);
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PPC_LD_OP(wz, ldl);
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PPC_LD_OP(ha_le, ld16rs);
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PPC_LD_OP(hz_le, ld16r);
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PPC_LD_OP(wz_le, ld32r);
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/*** Integer store ***/
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PPC_ST_OP(b, stb);
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PPC_ST_OP(h, stw);
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PPC_ST_OP(w, stl);
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PPC_ST_OP(h_le, st16r);
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PPC_ST_OP(w_le, st32r);
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/*** Integer load and store with byte reverse ***/
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PPC_LD_OP(hbr, ld16r);
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PPC_LD_OP(wbr, ld32r);
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PPC_ST_OP(hbr, st16r);
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PPC_ST_OP(wbr, st32r);
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PPC_LD_OP(hbr_le, lduw);
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PPC_LD_OP(wbr_le, ldl);
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PPC_ST_OP(hbr_le, stw);
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PPC_ST_OP(wbr_le, stl);
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/*** Integer load and store multiple ***/
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PPC_OP(glue(lmw, MEMSUFFIX))
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{
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int dst = PARAM(1);
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for (; dst < 32; dst++, T0 += 4) {
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ugpr(dst) = glue(ldl, MEMSUFFIX)(T0);
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}
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RETURN();
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}
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PPC_OP(glue(stmw, MEMSUFFIX))
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{
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int src = PARAM(1);
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for (; src < 32; src++, T0 += 4) {
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glue(stl, MEMSUFFIX)(T0, ugpr(src));
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}
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RETURN();
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}
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PPC_OP(glue(lmw_le, MEMSUFFIX))
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{
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int dst = PARAM(1);
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for (; dst < 32; dst++, T0 += 4) {
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ugpr(dst) = glue(ld32r, MEMSUFFIX)(T0);
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}
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RETURN();
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}
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PPC_OP(glue(stmw_le, MEMSUFFIX))
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{
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int src = PARAM(1);
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for (; src < 32; src++, T0 += 4) {
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glue(st32r, MEMSUFFIX)(T0, ugpr(src));
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}
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RETURN();
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}
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/*** Integer load and store strings ***/
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PPC_OP(glue(lswi, MEMSUFFIX))
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{
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glue(do_lsw, MEMSUFFIX)(PARAM(1));
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RETURN();
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}
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void glue(do_lsw_le, MEMSUFFIX) (int dst);
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PPC_OP(glue(lswi_le, MEMSUFFIX))
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{
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glue(do_lsw_le, MEMSUFFIX)(PARAM(1));
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RETURN();
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}
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/* PPC32 specification says we must generate an exception if
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* rA is in the range of registers to be loaded.
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* In an other hand, IBM says this is valid, but rA won't be loaded.
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* For now, I'll follow the spec...
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*/
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PPC_OP(glue(lswx, MEMSUFFIX))
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{
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if (T1 > 0) {
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if ((PARAM(1) < PARAM(2) && (PARAM(1) + T1) > PARAM(2)) ||
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(PARAM(1) < PARAM(3) && (PARAM(1) + T1) > PARAM(3))) {
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do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
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} else {
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glue(do_lsw, MEMSUFFIX)(PARAM(1));
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}
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}
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RETURN();
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}
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PPC_OP(glue(lswx_le, MEMSUFFIX))
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{
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if (T1 > 0) {
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if ((PARAM(1) < PARAM(2) && (PARAM(1) + T1) > PARAM(2)) ||
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(PARAM(1) < PARAM(3) && (PARAM(1) + T1) > PARAM(3))) {
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do_raise_exception_err(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
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} else {
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glue(do_lsw_le, MEMSUFFIX)(PARAM(1));
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}
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}
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RETURN();
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}
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PPC_OP(glue(stsw, MEMSUFFIX))
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{
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glue(do_stsw, MEMSUFFIX)(PARAM(1));
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RETURN();
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}
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void glue(do_stsw_le, MEMSUFFIX) (int src);
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PPC_OP(glue(stsw_le, MEMSUFFIX))
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{
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glue(do_stsw_le, MEMSUFFIX)(PARAM(1));
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RETURN();
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}
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/*** Floating-point store ***/
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#define PPC_STF_OP(name, op) \
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PPC_OP(glue(glue(st, name), MEMSUFFIX)) \
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{ \
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glue(op, MEMSUFFIX)(T0, FT1); \
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RETURN(); \
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}
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PPC_STF_OP(fd, stfq);
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PPC_STF_OP(fs, stfl);
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static inline void glue(stfqr, MEMSUFFIX) (target_ulong EA, double d)
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{
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union {
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double d;
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uint64_t u;
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} u;
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u.d = d;
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u.u = ((u.u & 0xFF00000000000000ULL) >> 56) |
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((u.u & 0x00FF000000000000ULL) >> 40) |
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((u.u & 0x0000FF0000000000ULL) >> 24) |
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((u.u & 0x000000FF00000000ULL) >> 8) |
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((u.u & 0x00000000FF000000ULL) << 8) |
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((u.u & 0x0000000000FF0000ULL) << 24) |
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((u.u & 0x000000000000FF00ULL) << 40) |
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((u.u & 0x00000000000000FFULL) << 56);
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glue(stfq, MEMSUFFIX)(EA, u.d);
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}
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static inline void glue(stflr, MEMSUFFIX) (target_ulong EA, float f)
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{
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union {
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float f;
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uint32_t u;
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} u;
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u.f = f;
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u.u = ((u.u & 0xFF000000UL) >> 24) |
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((u.u & 0x00FF0000ULL) >> 8) |
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((u.u & 0x0000FF00UL) << 8) |
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((u.u & 0x000000FFULL) << 24);
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glue(stfl, MEMSUFFIX)(EA, u.f);
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}
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PPC_STF_OP(fd_le, stfqr);
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PPC_STF_OP(fs_le, stflr);
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/*** Floating-point load ***/
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#define PPC_LDF_OP(name, op) \
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PPC_OP(glue(glue(l, name), MEMSUFFIX)) \
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{ \
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FT1 = glue(op, MEMSUFFIX)(T0); \
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RETURN(); \
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}
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PPC_LDF_OP(fd, ldfq);
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PPC_LDF_OP(fs, ldfl);
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static inline double glue(ldfqr, MEMSUFFIX) (target_ulong EA)
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{
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union {
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double d;
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uint64_t u;
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} u;
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u.d = glue(ldfq, MEMSUFFIX)(EA);
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u.u = ((u.u & 0xFF00000000000000ULL) >> 56) |
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((u.u & 0x00FF000000000000ULL) >> 40) |
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((u.u & 0x0000FF0000000000ULL) >> 24) |
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((u.u & 0x000000FF00000000ULL) >> 8) |
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((u.u & 0x00000000FF000000ULL) << 8) |
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((u.u & 0x0000000000FF0000ULL) << 24) |
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((u.u & 0x000000000000FF00ULL) << 40) |
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((u.u & 0x00000000000000FFULL) << 56);
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return u.d;
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}
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static inline float glue(ldflr, MEMSUFFIX) (target_ulong EA)
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{
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union {
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float f;
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uint32_t u;
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} u;
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u.f = glue(ldfl, MEMSUFFIX)(EA);
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u.u = ((u.u & 0xFF000000UL) >> 24) |
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((u.u & 0x00FF0000ULL) >> 8) |
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((u.u & 0x0000FF00UL) << 8) |
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((u.u & 0x000000FFULL) << 24);
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return u.f;
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}
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PPC_LDF_OP(fd_le, ldfqr);
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PPC_LDF_OP(fs_le, ldflr);
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/* Load and set reservation */
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PPC_OP(glue(lwarx, MEMSUFFIX))
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{
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if (T0 & 0x03) {
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do_raise_exception(EXCP_ALIGN);
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} else {
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T1 = glue(ldl, MEMSUFFIX)(T0);
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regs->reserve = T0;
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}
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RETURN();
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}
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PPC_OP(glue(lwarx_le, MEMSUFFIX))
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{
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if (T0 & 0x03) {
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do_raise_exception(EXCP_ALIGN);
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} else {
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T1 = glue(ld32r, MEMSUFFIX)(T0);
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regs->reserve = T0;
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}
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RETURN();
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}
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/* Store with reservation */
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PPC_OP(glue(stwcx, MEMSUFFIX))
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{
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if (T0 & 0x03) {
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do_raise_exception(EXCP_ALIGN);
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} else {
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if (regs->reserve != T0) {
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env->crf[0] = xer_ov;
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} else {
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glue(stl, MEMSUFFIX)(T0, T1);
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env->crf[0] = xer_ov | 0x02;
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}
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}
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regs->reserve = 0;
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RETURN();
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}
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PPC_OP(glue(stwcx_le, MEMSUFFIX))
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{
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if (T0 & 0x03) {
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do_raise_exception(EXCP_ALIGN);
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} else {
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if (regs->reserve != T0) {
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env->crf[0] = xer_ov;
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} else {
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glue(st32r, MEMSUFFIX)(T0, T1);
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env->crf[0] = xer_ov | 0x02;
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}
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}
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regs->reserve = 0;
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RETURN();
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}
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PPC_OP(glue(dcbz, MEMSUFFIX))
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{
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glue(stl, MEMSUFFIX)(T0 + 0x00, 0);
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glue(stl, MEMSUFFIX)(T0 + 0x04, 0);
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glue(stl, MEMSUFFIX)(T0 + 0x08, 0);
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glue(stl, MEMSUFFIX)(T0 + 0x0C, 0);
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glue(stl, MEMSUFFIX)(T0 + 0x10, 0);
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glue(stl, MEMSUFFIX)(T0 + 0x14, 0);
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glue(stl, MEMSUFFIX)(T0 + 0x18, 0);
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glue(stl, MEMSUFFIX)(T0 + 0x1C, 0);
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RETURN();
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}
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/* External access */
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PPC_OP(glue(eciwx, MEMSUFFIX))
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{
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T1 = glue(ldl, MEMSUFFIX)(T0);
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RETURN();
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}
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PPC_OP(glue(ecowx, MEMSUFFIX))
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{
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glue(stl, MEMSUFFIX)(T0, T1);
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RETURN();
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}
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PPC_OP(glue(eciwx_le, MEMSUFFIX))
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{
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T1 = glue(ld32r, MEMSUFFIX)(T0);
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RETURN();
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}
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PPC_OP(glue(ecowx_le, MEMSUFFIX))
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{
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glue(st32r, MEMSUFFIX)(T0, T1);
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RETURN();
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}
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#undef MEMSUFFIX
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