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4be403c815
The hassle and compile time overhead of maintaining both 32-bit and 64-bit capable source isn't worth the tiny performance advantage which is seen on a minority of configurations. Switch to compiling libhw only once, with target_phys_addr_t unconditionally typedefed to uint64_t. Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
279 lines
9.4 KiB
C
279 lines
9.4 KiB
C
/*
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* DMA helper functions
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*
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* Copyright (c) 2009 Red Hat
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*
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* This work is licensed under the terms of the GNU General Public License
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* (GNU GPL), version 2 or later.
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*/
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#ifndef DMA_H
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#define DMA_H
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#include <stdio.h>
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#include "hw/hw.h"
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#include "block.h"
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#include "kvm.h"
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typedef struct DMAContext DMAContext;
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typedef struct ScatterGatherEntry ScatterGatherEntry;
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typedef enum {
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DMA_DIRECTION_TO_DEVICE = 0,
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DMA_DIRECTION_FROM_DEVICE = 1,
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} DMADirection;
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struct QEMUSGList {
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ScatterGatherEntry *sg;
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int nsg;
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int nalloc;
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size_t size;
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DMAContext *dma;
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};
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#ifndef CONFIG_USER_ONLY
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/*
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* When an IOMMU is present, bus addresses become distinct from
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* CPU/memory physical addresses and may be a different size. Because
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* the IOVA size depends more on the bus than on the platform, we more
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* or less have to treat these as 64-bit always to cover all (or at
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* least most) cases.
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*/
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typedef uint64_t dma_addr_t;
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#define DMA_ADDR_BITS 64
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#define DMA_ADDR_FMT "%" PRIx64
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typedef int DMATranslateFunc(DMAContext *dma,
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dma_addr_t addr,
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target_phys_addr_t *paddr,
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target_phys_addr_t *len,
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DMADirection dir);
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typedef void* DMAMapFunc(DMAContext *dma,
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dma_addr_t addr,
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dma_addr_t *len,
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DMADirection dir);
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typedef void DMAUnmapFunc(DMAContext *dma,
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void *buffer,
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dma_addr_t len,
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DMADirection dir,
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dma_addr_t access_len);
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struct DMAContext {
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DMATranslateFunc *translate;
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DMAMapFunc *map;
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DMAUnmapFunc *unmap;
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};
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static inline void dma_barrier(DMAContext *dma, DMADirection dir)
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{
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/*
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* This is called before DMA read and write operations
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* unless the _relaxed form is used and is responsible
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* for providing some sane ordering of accesses vs
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* concurrently running VCPUs.
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*
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* Users of map(), unmap() or lower level st/ld_*
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* operations are responsible for providing their own
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* ordering via barriers.
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*
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* This primitive implementation does a simple smp_mb()
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* before each operation which provides pretty much full
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* ordering.
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*
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* A smarter implementation can be devised if needed to
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* use lighter barriers based on the direction of the
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* transfer, the DMA context, etc...
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*/
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if (kvm_enabled()) {
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smp_mb();
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}
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}
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static inline bool dma_has_iommu(DMAContext *dma)
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{
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return !!dma;
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}
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/* Checks that the given range of addresses is valid for DMA. This is
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* useful for certain cases, but usually you should just use
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* dma_memory_{read,write}() and check for errors */
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bool iommu_dma_memory_valid(DMAContext *dma, dma_addr_t addr, dma_addr_t len,
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DMADirection dir);
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static inline bool dma_memory_valid(DMAContext *dma,
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dma_addr_t addr, dma_addr_t len,
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DMADirection dir)
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{
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if (!dma_has_iommu(dma)) {
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return true;
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} else {
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return iommu_dma_memory_valid(dma, addr, len, dir);
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}
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}
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int iommu_dma_memory_rw(DMAContext *dma, dma_addr_t addr,
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void *buf, dma_addr_t len, DMADirection dir);
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static inline int dma_memory_rw_relaxed(DMAContext *dma, dma_addr_t addr,
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void *buf, dma_addr_t len,
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DMADirection dir)
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{
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if (!dma_has_iommu(dma)) {
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/* Fast-path for no IOMMU */
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cpu_physical_memory_rw(addr, buf, len,
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dir == DMA_DIRECTION_FROM_DEVICE);
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return 0;
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} else {
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return iommu_dma_memory_rw(dma, addr, buf, len, dir);
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}
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}
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static inline int dma_memory_read_relaxed(DMAContext *dma, dma_addr_t addr,
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void *buf, dma_addr_t len)
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{
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return dma_memory_rw_relaxed(dma, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
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}
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static inline int dma_memory_write_relaxed(DMAContext *dma, dma_addr_t addr,
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const void *buf, dma_addr_t len)
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{
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return dma_memory_rw_relaxed(dma, addr, (void *)buf, len,
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DMA_DIRECTION_FROM_DEVICE);
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}
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static inline int dma_memory_rw(DMAContext *dma, dma_addr_t addr,
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void *buf, dma_addr_t len,
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DMADirection dir)
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{
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dma_barrier(dma, dir);
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return dma_memory_rw_relaxed(dma, addr, buf, len, dir);
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}
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static inline int dma_memory_read(DMAContext *dma, dma_addr_t addr,
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void *buf, dma_addr_t len)
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{
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return dma_memory_rw(dma, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
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}
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static inline int dma_memory_write(DMAContext *dma, dma_addr_t addr,
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const void *buf, dma_addr_t len)
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{
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return dma_memory_rw(dma, addr, (void *)buf, len,
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DMA_DIRECTION_FROM_DEVICE);
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}
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int iommu_dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c,
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dma_addr_t len);
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int dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c, dma_addr_t len);
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void *iommu_dma_memory_map(DMAContext *dma,
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dma_addr_t addr, dma_addr_t *len,
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DMADirection dir);
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static inline void *dma_memory_map(DMAContext *dma,
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dma_addr_t addr, dma_addr_t *len,
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DMADirection dir)
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{
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if (!dma_has_iommu(dma)) {
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target_phys_addr_t xlen = *len;
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void *p;
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p = cpu_physical_memory_map(addr, &xlen,
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dir == DMA_DIRECTION_FROM_DEVICE);
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*len = xlen;
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return p;
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} else {
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return iommu_dma_memory_map(dma, addr, len, dir);
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}
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}
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void iommu_dma_memory_unmap(DMAContext *dma,
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void *buffer, dma_addr_t len,
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DMADirection dir, dma_addr_t access_len);
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static inline void dma_memory_unmap(DMAContext *dma,
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void *buffer, dma_addr_t len,
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DMADirection dir, dma_addr_t access_len)
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{
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if (!dma_has_iommu(dma)) {
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cpu_physical_memory_unmap(buffer, (target_phys_addr_t)len,
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dir == DMA_DIRECTION_FROM_DEVICE,
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access_len);
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} else {
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iommu_dma_memory_unmap(dma, buffer, len, dir, access_len);
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}
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}
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#define DEFINE_LDST_DMA(_lname, _sname, _bits, _end) \
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static inline uint##_bits##_t ld##_lname##_##_end##_dma(DMAContext *dma, \
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dma_addr_t addr) \
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{ \
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uint##_bits##_t val; \
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dma_memory_read(dma, addr, &val, (_bits) / 8); \
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return _end##_bits##_to_cpu(val); \
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} \
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static inline void st##_sname##_##_end##_dma(DMAContext *dma, \
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dma_addr_t addr, \
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uint##_bits##_t val) \
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{ \
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val = cpu_to_##_end##_bits(val); \
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dma_memory_write(dma, addr, &val, (_bits) / 8); \
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}
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static inline uint8_t ldub_dma(DMAContext *dma, dma_addr_t addr)
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{
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uint8_t val;
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dma_memory_read(dma, addr, &val, 1);
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return val;
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}
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static inline void stb_dma(DMAContext *dma, dma_addr_t addr, uint8_t val)
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{
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dma_memory_write(dma, addr, &val, 1);
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}
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DEFINE_LDST_DMA(uw, w, 16, le);
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DEFINE_LDST_DMA(l, l, 32, le);
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DEFINE_LDST_DMA(q, q, 64, le);
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DEFINE_LDST_DMA(uw, w, 16, be);
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DEFINE_LDST_DMA(l, l, 32, be);
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DEFINE_LDST_DMA(q, q, 64, be);
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#undef DEFINE_LDST_DMA
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void dma_context_init(DMAContext *dma, DMATranslateFunc translate,
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DMAMapFunc map, DMAUnmapFunc unmap);
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struct ScatterGatherEntry {
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dma_addr_t base;
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dma_addr_t len;
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};
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void qemu_sglist_init(QEMUSGList *qsg, int alloc_hint, DMAContext *dma);
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void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len);
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void qemu_sglist_destroy(QEMUSGList *qsg);
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#endif
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typedef BlockDriverAIOCB *DMAIOFunc(BlockDriverState *bs, int64_t sector_num,
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QEMUIOVector *iov, int nb_sectors,
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BlockDriverCompletionFunc *cb, void *opaque);
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BlockDriverAIOCB *dma_bdrv_io(BlockDriverState *bs,
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QEMUSGList *sg, uint64_t sector_num,
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DMAIOFunc *io_func, BlockDriverCompletionFunc *cb,
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void *opaque, DMADirection dir);
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BlockDriverAIOCB *dma_bdrv_read(BlockDriverState *bs,
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QEMUSGList *sg, uint64_t sector,
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BlockDriverCompletionFunc *cb, void *opaque);
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BlockDriverAIOCB *dma_bdrv_write(BlockDriverState *bs,
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QEMUSGList *sg, uint64_t sector,
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BlockDriverCompletionFunc *cb, void *opaque);
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uint64_t dma_buf_read(uint8_t *ptr, int32_t len, QEMUSGList *sg);
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uint64_t dma_buf_write(uint8_t *ptr, int32_t len, QEMUSGList *sg);
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void dma_acct_start(BlockDriverState *bs, BlockAcctCookie *cookie,
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QEMUSGList *sg, enum BlockAcctType type);
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#endif
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