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9793212bb0
Add a qemu_irq_split() function which allows a board to wire a single GPIO output up to two GPIO inputs. This is needed for realview boards, where the MMC card status is visible both in a system register and via a PL061 GPIO module. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
93 lines
2.6 KiB
C
93 lines
2.6 KiB
C
/*
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* QEMU IRQ/GPIO common code.
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*
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* Copyright (c) 2007 CodeSourcery.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu-common.h"
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#include "irq.h"
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struct IRQState {
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qemu_irq_handler handler;
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void *opaque;
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int n;
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};
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void qemu_set_irq(qemu_irq irq, int level)
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{
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if (!irq)
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return;
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irq->handler(irq->opaque, irq->n, level);
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}
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qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n)
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{
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qemu_irq *s;
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struct IRQState *p;
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int i;
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s = (qemu_irq *)qemu_mallocz(sizeof(qemu_irq) * n);
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p = (struct IRQState *)qemu_mallocz(sizeof(struct IRQState) * n);
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for (i = 0; i < n; i++) {
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p->handler = handler;
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p->opaque = opaque;
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p->n = i;
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s[i] = p;
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p++;
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}
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return s;
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}
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void qemu_free_irqs(qemu_irq *s)
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{
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qemu_free(s[0]);
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qemu_free(s);
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}
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static void qemu_notirq(void *opaque, int line, int level)
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{
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struct IRQState *irq = opaque;
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irq->handler(irq->opaque, irq->n, !level);
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}
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qemu_irq qemu_irq_invert(qemu_irq irq)
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{
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/* The default state for IRQs is low, so raise the output now. */
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qemu_irq_raise(irq);
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return qemu_allocate_irqs(qemu_notirq, irq, 1)[0];
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}
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static void qemu_splitirq(void *opaque, int line, int level)
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{
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struct IRQState **irq = opaque;
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irq[0]->handler(irq[0]->opaque, irq[0]->n, level);
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irq[1]->handler(irq[1]->opaque, irq[1]->n, level);
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}
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qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2)
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{
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qemu_irq *s = qemu_mallocz(2 * sizeof(qemu_irq));
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s[0] = irq1;
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s[1] = irq2;
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return qemu_allocate_irqs(qemu_splitirq, s, 1)[0];
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}
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