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qemu/hw/ssi
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Peter Crosthwaite b0b7ae6259 xilinx_spips: lqspi: Fix byte/misaligned access 
The LQSPI bus attachment supports byte/halfword and misaligned
accesses. Fixed. Refactored the LQSPI cache to be byte-wise
instead of word wise accordingly.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Message-id: 5ec47b13563ad2d22105a1f26186d7756718394b.1369117359.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2013-06-03 17:17:44 +01:00
..
Makefile.objs hw: move SSI controllers to hw/ssi/, configure via default-configs/ 2013-04-08 18:13:13 +02:00
omap_spi.c hw: move SSI controllers to hw/ssi/, configure via default-configs/ 2013-04-08 18:13:13 +02:00
pl022.c hw: move target-independent files to subdirectories 2013-04-08 18:13:12 +02:00
ssi.c hw: move target-independent files to subdirectories 2013-04-08 18:13:12 +02:00
xilinx_spi.c hw: move SSI controllers to hw/ssi/, configure via default-configs/ 2013-04-08 18:13:13 +02:00
xilinx_spips.c xilinx_spips: lqspi: Fix byte/misaligned access 2013-06-03 17:17:44 +01:00