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9fdc60bf55
Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6662 c046a42c-6fe2-441c-8c8c-71466251a162
45 lines
1.5 KiB
C
45 lines
1.5 KiB
C
/* PowerPC hardware exceptions management helpers */
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typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
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typedef struct clk_setup_t clk_setup_t;
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struct clk_setup_t {
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clk_setup_cb cb;
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void *opaque;
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};
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static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
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{
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if (clk->cb != NULL)
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(*clk->cb)(clk->opaque, freq);
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}
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clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
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/* Embedded PowerPC DCR management */
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typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
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typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
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int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
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int (*dcr_write_error)(int dcrn));
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int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
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dcr_read_cb drc_read, dcr_write_cb dcr_write);
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clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
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/* Embedded PowerPC reset */
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void ppc40x_core_reset (CPUState *env);
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void ppc40x_chip_reset (CPUState *env);
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void ppc40x_system_reset (CPUState *env);
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void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
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extern CPUWriteMemoryFunc *PPC_io_write[];
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extern CPUReadMemoryFunc *PPC_io_read[];
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void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
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void ppc40x_irq_init (CPUState *env);
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void ppce500_irq_init (CPUState *env);
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void ppc6xx_irq_init (CPUState *env);
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void ppc970_irq_init (CPUState *env);
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/* PPC machines for OpenBIOS */
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enum {
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ARCH_PREP = 0,
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ARCH_MAC99,
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ARCH_HEATHROW,
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};
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