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	 07f35073c6
			
		
	
	
		07f35073c6
		
	
	
	
	
		
			
			Signed-off-by: Dong Xu Wang <wdongxu@linux.vnet.ibm.com> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
		
			
				
	
	
		
			183 lines
		
	
	
		
			7.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			183 lines
		
	
	
		
			7.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| #ifndef CPU_COMMON_H
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| #define CPU_COMMON_H 1
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| 
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| /* CPU interfaces that are target independent.  */
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| 
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| #ifdef TARGET_PHYS_ADDR_BITS
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| #include "targphys.h"
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| #endif
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| 
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| #ifndef NEED_CPU_H
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| #include "poison.h"
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| #endif
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| 
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| #include "bswap.h"
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| #include "qemu-queue.h"
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| 
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| #if !defined(CONFIG_USER_ONLY)
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| 
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| enum device_endian {
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|     DEVICE_NATIVE_ENDIAN,
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|     DEVICE_BIG_ENDIAN,
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|     DEVICE_LITTLE_ENDIAN,
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| };
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| 
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| /* address in the RAM (different from a physical address) */
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| #if defined(CONFIG_XEN_BACKEND) && TARGET_PHYS_ADDR_BITS == 64
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| typedef uint64_t ram_addr_t;
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| #  define RAM_ADDR_MAX UINT64_MAX
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| #  define RAM_ADDR_FMT "%" PRIx64
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| #else
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| typedef unsigned long ram_addr_t;
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| #  define RAM_ADDR_MAX ULONG_MAX
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| #  define RAM_ADDR_FMT "%lx"
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| #endif
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| 
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| /* memory API */
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| 
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| typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
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| typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
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| 
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| void cpu_register_physical_memory_log(target_phys_addr_t start_addr,
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|                                       ram_addr_t size,
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|                                       ram_addr_t phys_offset,
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|                                       ram_addr_t region_offset,
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|                                       bool log_dirty);
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| 
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| static inline void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
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|                                                        ram_addr_t size,
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|                                                        ram_addr_t phys_offset,
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|                                                        ram_addr_t region_offset)
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| {
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|     cpu_register_physical_memory_log(start_addr, size, phys_offset,
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|                                      region_offset, false);
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| }
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| 
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| static inline void cpu_register_physical_memory(target_phys_addr_t start_addr,
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|                                                 ram_addr_t size,
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|                                                 ram_addr_t phys_offset)
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| {
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|     cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0);
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| }
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| 
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| ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
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| ram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name,
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|                         ram_addr_t size, void *host);
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| ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size);
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| void qemu_ram_free(ram_addr_t addr);
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| void qemu_ram_free_from_ptr(ram_addr_t addr);
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| void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
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| /* This should only be used for ram local to a device.  */
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| void *qemu_get_ram_ptr(ram_addr_t addr);
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| void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size);
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| /* Same but slower, to use for migration, where the order of
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|  * RAMBlocks must not change. */
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| void *qemu_safe_ram_ptr(ram_addr_t addr);
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| void qemu_put_ram_ptr(void *addr);
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| /* This should not be used by devices.  */
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| int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr);
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| ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);
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| 
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| int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
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|                            CPUWriteMemoryFunc * const *mem_write,
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|                            void *opaque, enum device_endian endian);
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| void cpu_unregister_io_memory(int table_address);
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| 
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| void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
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|                             int len, int is_write);
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| static inline void cpu_physical_memory_read(target_phys_addr_t addr,
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|                                             void *buf, int len)
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| {
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|     cpu_physical_memory_rw(addr, buf, len, 0);
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| }
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| static inline void cpu_physical_memory_write(target_phys_addr_t addr,
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|                                              const void *buf, int len)
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| {
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|     cpu_physical_memory_rw(addr, (void *)buf, len, 1);
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| }
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| void *cpu_physical_memory_map(target_phys_addr_t addr,
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|                               target_phys_addr_t *plen,
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|                               int is_write);
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| void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
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|                                int is_write, target_phys_addr_t access_len);
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| void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
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| void cpu_unregister_map_client(void *cookie);
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| 
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| struct CPUPhysMemoryClient;
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| typedef struct CPUPhysMemoryClient CPUPhysMemoryClient;
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| struct CPUPhysMemoryClient {
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|     void (*set_memory)(struct CPUPhysMemoryClient *client,
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|                        target_phys_addr_t start_addr,
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|                        ram_addr_t size,
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|                        ram_addr_t phys_offset,
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|                        bool log_dirty);
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|     int (*sync_dirty_bitmap)(struct CPUPhysMemoryClient *client,
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|                              target_phys_addr_t start_addr,
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|                              target_phys_addr_t end_addr);
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|     int (*migration_log)(struct CPUPhysMemoryClient *client,
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|                          int enable);
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|     int (*log_start)(struct CPUPhysMemoryClient *client,
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|                      target_phys_addr_t phys_addr, ram_addr_t size);
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|     int (*log_stop)(struct CPUPhysMemoryClient *client,
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|                     target_phys_addr_t phys_addr, ram_addr_t size);
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|     QLIST_ENTRY(CPUPhysMemoryClient) list;
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| };
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| 
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| void cpu_register_phys_memory_client(CPUPhysMemoryClient *);
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| void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *);
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| 
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| /* Coalesced MMIO regions are areas where write operations can be reordered.
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|  * This usually implies that write operations are side-effect free.  This allows
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|  * batching which can make a major impact on performance when using
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|  * virtualization.
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|  */
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| void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
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| 
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| void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
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| 
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| void qemu_flush_coalesced_mmio_buffer(void);
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| 
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| uint32_t ldub_phys(target_phys_addr_t addr);
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| uint32_t lduw_le_phys(target_phys_addr_t addr);
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| uint32_t lduw_be_phys(target_phys_addr_t addr);
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| uint32_t ldl_le_phys(target_phys_addr_t addr);
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| uint32_t ldl_be_phys(target_phys_addr_t addr);
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| uint64_t ldq_le_phys(target_phys_addr_t addr);
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| uint64_t ldq_be_phys(target_phys_addr_t addr);
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| void stb_phys(target_phys_addr_t addr, uint32_t val);
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| void stw_le_phys(target_phys_addr_t addr, uint32_t val);
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| void stw_be_phys(target_phys_addr_t addr, uint32_t val);
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| void stl_le_phys(target_phys_addr_t addr, uint32_t val);
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| void stl_be_phys(target_phys_addr_t addr, uint32_t val);
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| void stq_le_phys(target_phys_addr_t addr, uint64_t val);
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| void stq_be_phys(target_phys_addr_t addr, uint64_t val);
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| 
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| #ifdef NEED_CPU_H
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| uint32_t lduw_phys(target_phys_addr_t addr);
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| uint32_t ldl_phys(target_phys_addr_t addr);
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| uint64_t ldq_phys(target_phys_addr_t addr);
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| void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
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| void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
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| void stw_phys(target_phys_addr_t addr, uint32_t val);
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| void stl_phys(target_phys_addr_t addr, uint32_t val);
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| void stq_phys(target_phys_addr_t addr, uint64_t val);
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| #endif
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| 
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| void cpu_physical_memory_write_rom(target_phys_addr_t addr,
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|                                    const uint8_t *buf, int len);
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| 
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| #define IO_MEM_SHIFT       3
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| 
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| #define IO_MEM_RAM         (0 << IO_MEM_SHIFT) /* hardcoded offset */
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| #define IO_MEM_ROM         (1 << IO_MEM_SHIFT) /* hardcoded offset */
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| #define IO_MEM_UNASSIGNED  (2 << IO_MEM_SHIFT)
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| #define IO_MEM_NOTDIRTY    (3 << IO_MEM_SHIFT)
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| 
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| /* Acts like a ROM when read and like a device when written.  */
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| #define IO_MEM_ROMD        (1)
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| #define IO_MEM_SUBPAGE     (2)
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| 
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| #endif
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| 
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| #endif /* !CPU_COMMON_H */
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