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ce4fc986e5
The facility to use/unuse vectors dynamically is helpful
for virtio but little else: everyone just seems to use
vectors in their init function.
Avoid clearing msix vector use info on reset and load.
For virtio, clear it explicitly.
This should fix regressions reported with ivshmem - though
I didn't test this, I verified that virtio keeps
working like it did.
Tested-by: Cam Macdonell <cam@cs.ualberta.ca>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
(cherry picked from commit 3cac001e5a)
Conflicts:
hw/msix.c
hw/virtio-pci.c
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
426 lines
12 KiB
C
426 lines
12 KiB
C
/*
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* MSI-X device support
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*
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* This module includes support for MSI-X in pci devices.
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*
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* Author: Michael S. Tsirkin <mst@redhat.com>
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*
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* Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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*
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* Contributions after 2012-01-13 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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*/
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#include "hw.h"
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#include "msi.h"
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#include "msix.h"
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#include "pci.h"
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#include "range.h"
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#define MSIX_CAP_LENGTH 12
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/* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
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#define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
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#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
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#define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)
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/* How much space does an MSIX table need. */
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/* The spec requires giving the table structure
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* a 4K aligned region all by itself. */
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#define MSIX_PAGE_SIZE 0x1000
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/* Reserve second half of the page for pending bits */
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#define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
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#define MSIX_MAX_ENTRIES 32
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/* Add MSI-X capability to the config space for the device. */
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/* Given a bar and its size, add MSI-X table on top of it
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* and fill MSI-X capability in the config space.
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* Original bar size must be a power of 2 or 0.
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* New bar size is returned. */
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static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
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unsigned bar_nr, unsigned bar_size)
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{
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int config_offset;
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uint8_t *config;
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uint32_t new_size;
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if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1)
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return -EINVAL;
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if (bar_size > 0x80000000)
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return -ENOSPC;
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/* Add space for MSI-X structures */
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if (!bar_size) {
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new_size = MSIX_PAGE_SIZE;
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} else if (bar_size < MSIX_PAGE_SIZE) {
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bar_size = MSIX_PAGE_SIZE;
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new_size = MSIX_PAGE_SIZE * 2;
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} else {
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new_size = bar_size * 2;
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}
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pdev->msix_bar_size = new_size;
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config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX,
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0, MSIX_CAP_LENGTH);
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if (config_offset < 0)
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return config_offset;
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config = pdev->config + config_offset;
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pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
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/* Table on top of BAR */
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pci_set_long(config + PCI_MSIX_TABLE, bar_size | bar_nr);
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/* Pending bits on top of that */
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pci_set_long(config + PCI_MSIX_PBA, (bar_size + MSIX_PAGE_PENDING) |
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bar_nr);
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pdev->msix_cap = config_offset;
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/* Make flags bit writable. */
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pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
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MSIX_MASKALL_MASK;
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pdev->msix_function_masked = true;
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return 0;
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}
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static uint64_t msix_mmio_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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PCIDevice *dev = opaque;
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unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
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void *page = dev->msix_table_page;
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return pci_get_long(page + offset);
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}
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static uint8_t msix_pending_mask(int vector)
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{
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return 1 << (vector % 8);
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}
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static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
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{
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return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
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}
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static int msix_is_pending(PCIDevice *dev, int vector)
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{
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return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
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}
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static void msix_set_pending(PCIDevice *dev, int vector)
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{
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*msix_pending_byte(dev, vector) |= msix_pending_mask(vector);
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}
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static void msix_clr_pending(PCIDevice *dev, int vector)
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{
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*msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
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}
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static bool msix_vector_masked(PCIDevice *dev, int vector, bool fmask)
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{
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unsigned offset = vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
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return fmask || dev->msix_table_page[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
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}
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static bool msix_is_masked(PCIDevice *dev, int vector)
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{
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return msix_vector_masked(dev, vector, dev->msix_function_masked);
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}
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static void msix_handle_mask_update(PCIDevice *dev, int vector, bool was_masked)
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{
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bool is_masked = msix_is_masked(dev, vector);
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if (is_masked == was_masked) {
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return;
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}
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if (!is_masked && msix_is_pending(dev, vector)) {
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msix_clr_pending(dev, vector);
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msix_notify(dev, vector);
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}
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}
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static void msix_update_function_masked(PCIDevice *dev)
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{
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dev->msix_function_masked = !msix_enabled(dev) ||
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(dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK);
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}
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/* Handle MSI-X capability config write. */
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void msix_write_config(PCIDevice *dev, uint32_t addr,
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uint32_t val, int len)
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{
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unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
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int vector;
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bool was_masked;
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if (!range_covers_byte(addr, len, enable_pos)) {
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return;
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}
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was_masked = dev->msix_function_masked;
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msix_update_function_masked(dev);
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if (!msix_enabled(dev)) {
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return;
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}
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pci_device_deassert_intx(dev);
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if (dev->msix_function_masked == was_masked) {
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return;
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}
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for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
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msix_handle_mask_update(dev, vector,
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msix_vector_masked(dev, vector, was_masked));
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}
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}
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static void msix_mmio_write(void *opaque, target_phys_addr_t addr,
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uint64_t val, unsigned size)
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{
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PCIDevice *dev = opaque;
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unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
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int vector = offset / PCI_MSIX_ENTRY_SIZE;
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bool was_masked;
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/* MSI-X page includes a read-only PBA and a writeable Vector Control. */
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if (vector >= dev->msix_entries_nr) {
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return;
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}
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was_masked = msix_is_masked(dev, vector);
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pci_set_long(dev->msix_table_page + offset, val);
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msix_handle_mask_update(dev, vector, was_masked);
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}
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static const MemoryRegionOps msix_mmio_ops = {
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.read = msix_mmio_read,
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.write = msix_mmio_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void msix_mmio_setup(PCIDevice *d, MemoryRegion *bar)
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{
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uint8_t *config = d->config + d->msix_cap;
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uint32_t table = pci_get_long(config + PCI_MSIX_TABLE);
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uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
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/* TODO: for assigned devices, we'll want to make it possible to map
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* pending bits separately in case they are in a separate bar. */
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memory_region_add_subregion(bar, offset, &d->msix_mmio);
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}
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static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
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{
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int vector;
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for (vector = 0; vector < nentries; ++vector) {
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unsigned offset =
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vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
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dev->msix_table_page[offset] |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
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}
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}
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/* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
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* modified, it should be retrieved with msix_bar_size. */
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int msix_init(struct PCIDevice *dev, unsigned short nentries,
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MemoryRegion *bar,
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unsigned bar_nr, unsigned bar_size)
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{
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int ret;
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/* Nothing to do if MSI is not supported by interrupt controller */
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if (!msi_supported) {
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return -ENOTSUP;
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}
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if (nentries > MSIX_MAX_ENTRIES)
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return -EINVAL;
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dev->msix_entry_used = g_malloc0(MSIX_MAX_ENTRIES *
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sizeof *dev->msix_entry_used);
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dev->msix_table_page = g_malloc0(MSIX_PAGE_SIZE);
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msix_mask_all(dev, nentries);
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memory_region_init_io(&dev->msix_mmio, &msix_mmio_ops, dev,
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"msix", MSIX_PAGE_SIZE);
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dev->msix_entries_nr = nentries;
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ret = msix_add_config(dev, nentries, bar_nr, bar_size);
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if (ret)
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goto err_config;
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dev->cap_present |= QEMU_PCI_CAP_MSIX;
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msix_mmio_setup(dev, bar);
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return 0;
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err_config:
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dev->msix_entries_nr = 0;
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memory_region_destroy(&dev->msix_mmio);
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g_free(dev->msix_table_page);
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dev->msix_table_page = NULL;
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g_free(dev->msix_entry_used);
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dev->msix_entry_used = NULL;
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return ret;
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}
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static void msix_free_irq_entries(PCIDevice *dev)
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{
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int vector;
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for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
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dev->msix_entry_used[vector] = 0;
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msix_clr_pending(dev, vector);
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}
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}
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static void msix_clear_all_vectors(PCIDevice *dev)
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{
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int vector;
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for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
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msix_clr_pending(dev, vector);
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}
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}
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/* Clean up resources for the device. */
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int msix_uninit(PCIDevice *dev, MemoryRegion *bar)
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{
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if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
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return 0;
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pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
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dev->msix_cap = 0;
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msix_free_irq_entries(dev);
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dev->msix_entries_nr = 0;
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memory_region_del_subregion(bar, &dev->msix_mmio);
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memory_region_destroy(&dev->msix_mmio);
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g_free(dev->msix_table_page);
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dev->msix_table_page = NULL;
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g_free(dev->msix_entry_used);
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dev->msix_entry_used = NULL;
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dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
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return 0;
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}
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void msix_save(PCIDevice *dev, QEMUFile *f)
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{
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unsigned n = dev->msix_entries_nr;
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if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
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return;
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}
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qemu_put_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
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qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
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}
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/* Should be called after restoring the config space. */
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void msix_load(PCIDevice *dev, QEMUFile *f)
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{
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unsigned n = dev->msix_entries_nr;
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if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
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return;
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}
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msix_clear_all_vectors(dev);
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qemu_get_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
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qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
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msix_update_function_masked(dev);
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}
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/* Does device support MSI-X? */
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int msix_present(PCIDevice *dev)
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{
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return dev->cap_present & QEMU_PCI_CAP_MSIX;
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}
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/* Is MSI-X enabled? */
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int msix_enabled(PCIDevice *dev)
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{
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return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
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(dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
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MSIX_ENABLE_MASK);
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}
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/* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
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uint32_t msix_bar_size(PCIDevice *dev)
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{
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return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
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dev->msix_bar_size : 0;
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}
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/* Send an MSI-X message */
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void msix_notify(PCIDevice *dev, unsigned vector)
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{
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uint8_t *table_entry = dev->msix_table_page + vector * PCI_MSIX_ENTRY_SIZE;
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uint64_t address;
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uint32_t data;
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if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
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return;
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if (msix_is_masked(dev, vector)) {
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msix_set_pending(dev, vector);
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return;
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}
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address = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR);
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data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA);
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stl_le_phys(address, data);
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}
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void msix_reset(PCIDevice *dev)
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{
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if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
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return;
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msix_clear_all_vectors(dev);
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dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
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~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
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memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
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msix_mask_all(dev, dev->msix_entries_nr);
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}
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/* PCI spec suggests that devices make it possible for software to configure
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* less vectors than supported by the device, but does not specify a standard
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* mechanism for devices to do so.
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*
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* We support this by asking devices to declare vectors software is going to
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* actually use, and checking this on the notification path. Devices that
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* don't want to follow the spec suggestion can declare all vectors as used. */
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/* Mark vector as used. */
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int msix_vector_use(PCIDevice *dev, unsigned vector)
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{
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if (vector >= dev->msix_entries_nr)
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return -EINVAL;
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dev->msix_entry_used[vector]++;
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return 0;
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}
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/* Mark vector as unused. */
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void msix_vector_unuse(PCIDevice *dev, unsigned vector)
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{
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if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
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return;
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}
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if (--dev->msix_entry_used[vector]) {
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return;
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}
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msix_clr_pending(dev, vector);
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}
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void msix_unuse_all_vectors(PCIDevice *dev)
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{
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if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
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return;
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msix_free_irq_entries(dev);
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}
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