Commit Graph

4 Commits

Author SHA1 Message Date
Stefan Weil
d80e20a1c3 tcp/mips: Change TCG_AREG0 (fp -> s0)
Register fp (frame pointer) is a bad choice for compilations
without optimisation, because the compiler makes heavy use
of this register (so the resulting code crashes).

Register s0 had been used for TCG_AREG1 in earlier releases,
but was no longer used and is now free for TCG_AREG0.

The resulting code works for compilations without
optimisation (tested with qemu mips in qemu mips
on x86 host).

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-14 01:02:24 +02:00
Aurelien Jarno
81b168a702 tcg/mips: fix branch offset during retranslation
Branch offsets should only be overwritten during relocation, to support
partial retranslation.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
(cherry picked from commit 6d8ff4d85c)
2010-03-29 02:11:35 +02:00
Aurelien Jarno
307331a42a tcg/mips: fix crash in tcg_out_qemu_ld()
The address register is overriden when it corresponds to v0 and the fast
path is taken, which leads to a crash. Fix that by using the a0 register
instead.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
(cherry picked from commit cca1af8c4d)
2010-02-09 23:29:44 +01:00
Aurelien Jarno
afa05235a5 tcg: initial mips support
Based on a patch from Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>

A few words about design choices:
* Two registers, at and t0, are reserved for TCG internal use. They are
  useful for bswap and 64-bit ops.
* Most ops supports a constant argument with value 0, which is actually
  mapped to the zero register.
* While the at register is available for constant loading, ops only
  support a limited range of constants. TCG does a better job doing the
  register allocation and constant loading by itself. There are plenty of
  registers available anyway.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-01 00:06:15 +00:00