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Fix ARM MCore secondary cpu boot

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Make MPCore secondary cpu initialization work with the new reset
handling.  Also change the inital FLAG value from 3 to zero to match
recent kenrels.

Signed-off-by: Paul Brook <paul@codesourcery.com>
This commit is contained in:
Paul Brook 2009-11-11 19:59:29 +00:00
parent 97fe84f5ef
commit be0f204aa0
3 changed files with 27 additions and 9 deletions
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4
hw/arm_boot.c
View File

@ -39,8 +39,8 @@ static uint32_t smpboot[] = {
0xe3800030, /* orr r0, #0x30 */ 0xe3800030, /* orr r0, #0x30 */
0xe320f003, /* wfi */ 0xe320f003, /* wfi */
0xe5901000, /* ldr r1, [r0] */ 0xe5901000, /* ldr r1, [r0] */
0xe3110003, /* tst r1, #3 */ 0xe1110001, /* tst r1, r1 */
0x1afffffb, /* bne <wfi> */ 0x0afffffb, /* beq <wfi> */
0xe12fff11 /* bx r1 */ 0xe12fff11 /* bx r1 */
}; };

16
hw/arm_sysctl.c
View File

@ -27,6 +27,18 @@ typedef struct {
uint32_t resetlevel; uint32_t resetlevel;
} arm_sysctl_state; } arm_sysctl_state;
static void arm_sysctl_reset(DeviceState *d)
{
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sysbus_from_qdev(d));
s->leds = 0;
s->lockval = 0;
s->cfgdata1 = 0;
s->cfgdata2 = 0;
s->flags = 0;
s->resetlevel = 0;
}
static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset) static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
{ {
arm_sysctl_state *s = (arm_sysctl_state *)opaque; arm_sysctl_state *s = (arm_sysctl_state *)opaque;
@ -195,9 +207,6 @@ static int arm_sysctl_init1(SysBusDevice *dev)
arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev); arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
int iomemtype; int iomemtype;
/* The MPcore bootloader uses these flags to start secondary CPUs.
We don't use a bootloader, so do this here. */
s->flags = 3;
iomemtype = cpu_register_io_memory(arm_sysctl_readfn, iomemtype = cpu_register_io_memory(arm_sysctl_readfn,
arm_sysctl_writefn, s); arm_sysctl_writefn, s);
sysbus_init_mmio(dev, 0x1000, iomemtype); sysbus_init_mmio(dev, 0x1000, iomemtype);
@ -220,6 +229,7 @@ static SysBusDeviceInfo arm_sysctl_info = {
.init = arm_sysctl_init1, .init = arm_sysctl_init1,
.qdev.name = "realview_sysctl", .qdev.name = "realview_sysctl",
.qdev.size = sizeof(arm_sysctl_state), .qdev.size = sizeof(arm_sysctl_state),
.qdev.reset = arm_sysctl_reset,
.qdev.props = (Property[]) { .qdev.props = (Property[]) {
DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0), DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),

16
hw/realview.c
View File

@ -24,6 +24,17 @@ static struct arm_boot_info realview_binfo = {
.board_id = 0x33b, .board_id = 0x33b,
}; };
static void secondary_cpu_reset(void *opaque)
{
CPUState *env = opaque;
cpu_reset(env);
/* Set entry point for secondary CPUs. This assumes we're using
the init code from arm_boot.c. Real hardware resets all CPUs
the same. */
env->regs[15] = 0x80000000;
}
static void realview_init(ram_addr_t ram_size, static void realview_init(ram_addr_t ram_size,
const char *boot_device, const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline, const char *kernel_filename, const char *kernel_cmdline,
@ -59,10 +70,7 @@ static void realview_init(ram_addr_t ram_size,
irqp = arm_pic_init_cpu(env); irqp = arm_pic_init_cpu(env);
cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
if (n > 0) { if (n > 0) {
/* Set entry point for secondary CPUs. This assumes we're using qemu_register_reset(secondary_cpu_reset, env);
the init code from arm_boot.c. Real hardware resets all CPUs
the same. */
env->regs[15] = 0x80000000;
} }
} }