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mips: Break out cpu_mips_timer_expire

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Reorganize for future patches, no functional change.

Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
Edgar E. Iglesias 2011-01-18 00:07:49 +01:00
parent 4a6648f44e
commit b1dfe6437c
1 changed files with 22 additions and 14 deletions
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36
hw/mips_timer.c
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@ -42,16 +42,6 @@ uint32_t cpu_mips_get_random (CPUState *env)
} }
/* MIPS R4K timer */ /* MIPS R4K timer */
uint32_t cpu_mips_get_count (CPUState *env)
{
if (env->CP0_Cause & (1 << CP0Ca_DC))
return env->CP0_Count;
else
return env->CP0_Count +
(uint32_t)muldiv64(qemu_get_clock(vm_clock),
TIMER_FREQ, get_ticks_per_sec());
}
static void cpu_mips_timer_update(CPUState *env) static void cpu_mips_timer_update(CPUState *env)
{ {
uint64_t now, next; uint64_t now, next;
@ -64,6 +54,27 @@ static void cpu_mips_timer_update(CPUState *env)
qemu_mod_timer(env->timer, next); qemu_mod_timer(env->timer, next);
} }
/* Expire the timer. */
static void cpu_mips_timer_expire(CPUState *env)
{
cpu_mips_timer_update(env);
if (env->insn_flags & ISA_MIPS32R2) {
env->CP0_Cause |= 1 << CP0Ca_TI;
}
qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
}
uint32_t cpu_mips_get_count (CPUState *env)
{
if (env->CP0_Cause & (1 << CP0Ca_DC)) {
return env->CP0_Count;
} else {
return env->CP0_Count +
(uint32_t)muldiv64(qemu_get_clock(vm_clock),
TIMER_FREQ, get_ticks_per_sec());
}
}
void cpu_mips_store_count (CPUState *env, uint32_t count) void cpu_mips_store_count (CPUState *env, uint32_t count)
{ {
if (env->CP0_Cause & (1 << CP0Ca_DC)) if (env->CP0_Cause & (1 << CP0Ca_DC))
@ -116,11 +127,8 @@ static void mips_timer_cb (void *opaque)
the comparator value. Offset the count by one to avoid immediately the comparator value. Offset the count by one to avoid immediately
retriggering the callback before any virtual time has passed. */ retriggering the callback before any virtual time has passed. */
env->CP0_Count++; env->CP0_Count++;
cpu_mips_timer_update(env); cpu_mips_timer_expire(env);
env->CP0_Count--; env->CP0_Count--;
if (env->insn_flags & ISA_MIPS32R2)
env->CP0_Cause |= 1 << CP0Ca_TI;
qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
} }
void cpu_mips_clock_init (CPUState *env) void cpu_mips_clock_init (CPUState *env)