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Improve iommu debugging, use register names

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3114 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2007-08-11 07:49:55 +00:00
parent 8a93e02a93
commit 981a2e9906
1 changed files with 14 additions and 7 deletions
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21
hw/iommu.c
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@ -100,7 +100,7 @@ static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
saddr = (addr - s->addr) >> 2; saddr = (addr - s->addr) >> 2;
switch (saddr) { switch (saddr) {
default: default:
DPRINTF("read reg[%d] = %x\n", saddr, s->regs[saddr]); DPRINTF("read reg[%d] = %x\n", (int)saddr, s->regs[saddr]);
return s->regs[saddr]; return s->regs[saddr];
break; break;
} }
@ -113,7 +113,7 @@ static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val
target_phys_addr_t saddr; target_phys_addr_t saddr;
saddr = (addr - s->addr) >> 2; saddr = (addr - s->addr) >> 2;
DPRINTF("write reg[%d] = %x\n", saddr, val); DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
switch (saddr) { switch (saddr) {
case IOMMU_CTRL: case IOMMU_CTRL:
switch (val & IOMMU_CTRL_RNGE) { switch (val & IOMMU_CTRL_RNGE) {
@ -143,7 +143,7 @@ static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val
s->iostart = 0xffffffff80000000ULL; s->iostart = 0xffffffff80000000ULL;
break; break;
} }
DPRINTF("iostart = %llx\n", s->iostart); DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION); s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION);
break; break;
case IOMMU_BASE: case IOMMU_BASE:
@ -188,12 +188,19 @@ static CPUWriteMemoryFunc *iommu_mem_write[3] = {
static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr) static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
{ {
uint32_t iopte; uint32_t iopte, ret;
#ifdef DEBUG_IOMMU
target_phys_addr_t pa = addr;
#endif
iopte = s->regs[1] << 4; iopte = s->regs[IOMMU_BASE] << 4;
addr &= ~s->iostart; addr &= ~s->iostart;
iopte += (addr >> (PAGE_SHIFT - 2)) & ~3; iopte += (addr >> (PAGE_SHIFT - 2)) & ~3;
return ldl_phys(iopte); ret = ldl_phys(iopte);
DPRINTF("get flags addr " TARGET_FMT_plx " => pte %x, *ptes = %x\n", pa,
iopte, ret);
return ret;
} }
static target_phys_addr_t iommu_translate_pa(IOMMUState *s, static target_phys_addr_t iommu_translate_pa(IOMMUState *s,
@ -271,7 +278,7 @@ static void iommu_reset(void *opaque)
memset(s->regs, 0, IOMMU_NREGS * 4); memset(s->regs, 0, IOMMU_NREGS * 4);
s->iostart = 0; s->iostart = 0;
s->regs[0] = IOMMU_VERSION; s->regs[IOMMU_CTRL] = IOMMU_VERSION;
} }
void *iommu_init(target_phys_addr_t addr) void *iommu_init(target_phys_addr_t addr)