PL190 qdev conversion

Signed-off-by: Paul Brook <paul@codesourcery.com>

hw/pl190.c

@@ -7,8 +7,7 @@
  * This code is licenced under the GPL.
  */
 
-#include "hw.h"
+#include "sysbus.h"
-#include "primecell.h"
 
 /* The number of virtual priority levels.  16 user vectors plus the
    unvectored IRQ.  Chained interrupts would require an additional level
@@ -17,6 +16,7 @@
 #define PL190_NUM_PRIO 17
 
 typedef struct {
+    SysBusDevice busdev;
     uint32_t level;
     uint32_t soft_level;
     uint32_t irq_enable;
@@ -227,20 +227,24 @@ static void pl190_reset(pl190_state *s)
   pl190_update_vectors(s);
 }
 
-qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq)
+static void pl190_init(SysBusDevice *dev)
 {
-    pl190_state *s;
+    pl190_state *s = FROM_SYSBUS(pl190_state, dev);
-    qemu_irq *qi;
     int iomemtype;
 
-    s = (pl190_state *)qemu_mallocz(sizeof(pl190_state));
     iomemtype = cpu_register_io_memory(0, pl190_readfn,
                                        pl190_writefn, s);
-    cpu_register_physical_memory(base, 0x00001000, iomemtype);
+    sysbus_init_mmio(dev, 0x1000, iomemtype);
-    qi = qemu_allocate_irqs(pl190_set_irq, s, 32);
+    qdev_init_irq_sink(&dev->qdev, pl190_set_irq, 32);
-    s->irq = irq;
+    sysbus_init_irq(dev, &s->irq);
-    s->fiq = fiq;
+    sysbus_init_irq(dev, &s->fiq);
     pl190_reset(s);
     /* ??? Save/restore.  */
-    return qi;
 }
+
+static void pl190_register_devices(void)
+{
+    sysbus_register_dev("pl190", sizeof(pl190_state), pl190_init);
+}
+
+device_init(pl190_register_devices)

hw/primecell.h

@@ -17,9 +17,6 @@ qemu_irq *pl061_init(uint32_t base, qemu_irq irq, qemu_irq **out);
 /* pl080.c */
 void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
 
-/* pl190.c */
-qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
-
 /* realview_gic.c */
 qemu_irq *realview_gic_init(uint32_t base, qemu_irq parent_irq);
 
@@ -30,6 +27,6 @@ extern qemu_irq *mpcore_irq_init(qemu_irq *cpu_irq);
 void arm_sysctl_init(uint32_t base, uint32_t sys_id);
 
 /* versatile_pci.c */
-PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
+PCIBus *pci_vpb_init(qemu_irq *pic, int realview);
 
 #endif

hw/realview.c

@@ -100,7 +100,7 @@ static void realview_init(ram_addr_t ram_size,
 
     sysbus_create_simple("pl031", 0x10017000, pic[10]);
 
-    pci_bus = pci_vpb_init(pic, 48, 1);
+    pci_bus = pci_vpb_init(pic + 48, 1);
     if (usb_enabled) {
         usb_ohci_init_pci(pci_bus, 3, -1);
     }

hw/versatile_pci.c

@@ -79,8 +79,6 @@ static CPUReadMemoryFunc *pci_vpb_config_read[] = {
     &pci_vpb_config_readl,
 };
 
-static int pci_vpb_irq;
-
 static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
 {
     return irq_num;
@@ -88,18 +86,23 @@ static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
 
 static void pci_vpb_set_irq(qemu_irq *pic, int irq_num, int level)
 {
-    qemu_set_irq(pic[pci_vpb_irq + irq_num], level);
+    qemu_set_irq(pic[irq_num], level);
 }
 
-PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview)
+PCIBus *pci_vpb_init(qemu_irq *pic, int realview)
 {
     PCIBus *s;
     PCIDevice *d;
     int mem_config;
     uint32_t base;
     const char * name;
+    qemu_irq *irqs;
+    int i;
 
-    pci_vpb_irq = irq;
+    irqs = qemu_mallocz(sizeof(qemu_irq) * 4);
+    for (i = 0; i < 4; i++) {
+        irqs[i] = pic[i];
+    }
     if (realview) {
         base = 0x60000000;
         name = "RealView EB PCI Controller";
@@ -107,7 +110,7 @@ PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview)
         base = 0x40000000;
         name = "Versatile/PB PCI Controller";
     }
-    s = pci_register_bus(pci_vpb_set_irq, pci_vpb_map_irq, pic, 11 << 3, 4);
+    s = pci_register_bus(pci_vpb_set_irq, pci_vpb_map_irq, irqs, 11 << 3, 4);
     /* ??? Register memory space.  */
 
     mem_config = cpu_register_io_memory(0, pci_vpb_config_read,

hw/versatilepb.c

@@ -23,7 +23,7 @@ typedef struct vpb_sic_state
   uint32_t level;
   uint32_t mask;
   uint32_t pic_enable;
-  qemu_irq *parent;
+  qemu_irq parent[32];
   int irq;
 } vpb_sic_state;
 
@@ -133,10 +133,13 @@ static qemu_irq *vpb_sic_init(uint32_t base, qemu_irq *parent, int irq)
     vpb_sic_state *s;
     qemu_irq *qi;
     int iomemtype;
+    int i;
 
     s = (vpb_sic_state *)qemu_mallocz(sizeof(vpb_sic_state));
     qi = qemu_allocate_irqs(vpb_sic_set_irq, s, 32);
-    s->parent = parent;
+    for (i = 0; i < 32; i++) {
+        s->parent[i] = parent[i];
+    }
     s->irq = irq;
     iomemtype = cpu_register_io_memory(0, vpb_sic_readfn,
                                        vpb_sic_writefn, s);
@@ -161,8 +164,10 @@ static void versatile_init(ram_addr_t ram_size,
 {
     CPUState *env;
     ram_addr_t ram_offset;
-    qemu_irq *pic;
+    qemu_irq *cpu_pic;
+    qemu_irq pic[32];
     qemu_irq *sic;
+    DeviceState *dev;
     PCIBus *pci_bus;
     NICInfo *nd;
     int n;
@@ -181,14 +186,18 @@ static void versatile_init(ram_addr_t ram_size,
     cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
 
     arm_sysctl_init(0x10000000, 0x41007004);
-    pic = arm_pic_init_cpu(env);
+    cpu_pic = arm_pic_init_cpu(env);
-    pic = pl190_init(0x10140000, pic[0], pic[1]);
+    dev = sysbus_create_varargs("pl190", 0x10140000,
+                                cpu_pic[0], cpu_pic[1], NULL);
+    for (n = 0; n < 32; n++) {
+        pic[n] = qdev_get_irq_sink(dev, n);
+    }
     sic = vpb_sic_init(0x10003000, pic, 31);
 
     sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
     sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);
 
-    pci_bus = pci_vpb_init(sic, 27, 0);
+    pci_bus = pci_vpb_init(sic + 27, 0);
     /* The Versatile PCI bridge does not provide access to PCI IO space,
        so many of the qemu PCI devices are not useable.  */
     for(n = 0; n < nb_nics; n++) {