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pxa2xx_pic: convert to memory API
The ARM documentation say transfers between the cpu and the coprocessor are 32 bits wide. Use 4 as size for coprocessor read and writes. Signed-off-by: Benoit Canet <benoit.canet@gmail.com> Signed-off-by: Avi Kivity <avi@redhat.com>
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b755bde386
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@ -33,6 +33,7 @@
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typedef struct {
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typedef struct {
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SysBusDevice busdev;
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SysBusDevice busdev;
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MemoryRegion iomem;
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CPUState *cpu_env;
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CPUState *cpu_env;
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uint32_t int_enabled[2];
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uint32_t int_enabled[2];
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uint32_t int_pending[2];
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uint32_t int_pending[2];
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@ -115,7 +116,8 @@ static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState *s) {
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return ichp;
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return ichp;
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}
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}
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static uint32_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset)
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static uint64_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset,
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unsigned size)
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{
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{
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PXA2xxPICState *s = (PXA2xxPICState *) opaque;
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PXA2xxPICState *s = (PXA2xxPICState *) opaque;
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@ -155,7 +157,7 @@ static uint32_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset)
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}
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}
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static void pxa2xx_pic_mem_write(void *opaque, target_phys_addr_t offset,
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static void pxa2xx_pic_mem_write(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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uint64_t value, unsigned size)
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{
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{
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PXA2xxPICState *s = (PXA2xxPICState *) opaque;
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PXA2xxPICState *s = (PXA2xxPICState *) opaque;
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@ -214,7 +216,7 @@ static uint32_t pxa2xx_pic_cp_read(void *opaque, int op2, int reg, int crm)
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}
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}
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offset = pxa2xx_cp_reg_map[reg];
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offset = pxa2xx_cp_reg_map[reg];
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return pxa2xx_pic_mem_read(opaque, offset);
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return pxa2xx_pic_mem_read(opaque, offset, 4);
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}
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}
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static void pxa2xx_pic_cp_write(void *opaque, int op2, int reg, int crm,
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static void pxa2xx_pic_cp_write(void *opaque, int op2, int reg, int crm,
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@ -228,19 +230,13 @@ static void pxa2xx_pic_cp_write(void *opaque, int op2, int reg, int crm,
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}
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}
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offset = pxa2xx_cp_reg_map[reg];
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offset = pxa2xx_cp_reg_map[reg];
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pxa2xx_pic_mem_write(opaque, offset, value);
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pxa2xx_pic_mem_write(opaque, offset, value, 4);
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}
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}
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static CPUReadMemoryFunc * const pxa2xx_pic_readfn[] = {
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static const MemoryRegionOps pxa2xx_pic_ops = {
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pxa2xx_pic_mem_read,
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.read = pxa2xx_pic_mem_read,
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pxa2xx_pic_mem_read,
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.write = pxa2xx_pic_mem_write,
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pxa2xx_pic_mem_read,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static CPUWriteMemoryFunc * const pxa2xx_pic_writefn[] = {
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pxa2xx_pic_mem_write,
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pxa2xx_pic_mem_write,
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pxa2xx_pic_mem_write,
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};
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};
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static int pxa2xx_pic_post_load(void *opaque, int version_id)
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static int pxa2xx_pic_post_load(void *opaque, int version_id)
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@ -252,7 +248,6 @@ static int pxa2xx_pic_post_load(void *opaque, int version_id)
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DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
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DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
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{
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{
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DeviceState *dev = qdev_create(NULL, "pxa2xx_pic");
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DeviceState *dev = qdev_create(NULL, "pxa2xx_pic");
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int iomemtype;
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PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, sysbus_from_qdev(dev));
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PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, sysbus_from_qdev(dev));
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s->cpu_env = env;
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s->cpu_env = env;
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@ -269,9 +264,9 @@ DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
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qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);
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qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);
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/* Enable IC memory-mapped registers access. */
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/* Enable IC memory-mapped registers access. */
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iomemtype = cpu_register_io_memory(pxa2xx_pic_readfn,
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memory_region_init_io(&s->iomem, &pxa2xx_pic_ops, s,
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pxa2xx_pic_writefn, s, DEVICE_NATIVE_ENDIAN);
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"pxa2xx-pic", 0x00100000);
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sysbus_init_mmio(sysbus_from_qdev(dev), 0x00100000, iomemtype);
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sysbus_init_mmio_region(sysbus_from_qdev(dev), &s->iomem);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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/* Enable IC coprocessor access. */
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/* Enable IC coprocessor access. */
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