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target-arm: Add CP15 VBAR support

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Added Vector Base Address remapping on ARM v7.

Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
[PMM: removed spurious mask of value with 1<<31]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Nathan Rossi 2013-10-25 15:44:38 +01:00 committed by Edgar E. Iglesias
parent dacecf5485
commit 8641136c54
2 changed files with 22 additions and 0 deletions
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1
target-arm/cpu.h
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@ -176,6 +176,7 @@ typedef struct CPUARMState {
uint32_t c9_pmxevtyper; /* perf monitor event type */ uint32_t c9_pmxevtyper; /* perf monitor event type */
uint32_t c9_pmuserenr; /* perf monitor user enable */ uint32_t c9_pmuserenr; /* perf monitor user enable */
uint32_t c9_pminten; /* perf monitor interrupt enables */ uint32_t c9_pminten; /* perf monitor interrupt enables */
uint32_t c12_vbar; /* vector base address register */
uint32_t c13_fcse; /* FCSE PID. */ uint32_t c13_fcse; /* FCSE PID. */
uint32_t c13_context; /* Context ID. */ uint32_t c13_context; /* Context ID. */
uint32_t c13_tls1; /* User RW Thread register. */ uint32_t c13_tls1; /* User RW Thread register. */

21
target-arm/helper.c
View File

@ -537,6 +537,13 @@ static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
return 0; return 0;
} }
static int vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
env->cp15.c12_vbar = value & ~0x1Ful;
return 0;
}
static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri, static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t *value) uint64_t *value)
{ {
@ -622,6 +629,10 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
.resetvalue = 0, .writefn = pmintenclr_write, }, .resetvalue = 0, .writefn = pmintenclr_write, },
{ .name = "VBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .writefn = vbar_write,
.fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
.resetvalue = 0 },
{ .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
.resetvalue = 0, }, .resetvalue = 0, },
@ -2470,7 +2481,17 @@ void arm_cpu_do_interrupt(CPUState *cs)
} }
/* High vectors. */ /* High vectors. */
if (env->cp15.c1_sys & (1 << 13)) { if (env->cp15.c1_sys & (1 << 13)) {
/* when enabled, base address cannot be remapped. */
addr += 0xffff0000; addr += 0xffff0000;
} else {
/* ARM v7 architectures provide a vector base address register to remap
* the interrupt vector table.
* This register is only followed in non-monitor mode, and has a secure
* and un-secure copy. Since the cpu is always in a un-secure operation
* and is never in monitor mode this feature is always active.
* Note: only bits 31:5 are valid.
*/
addr += env->cp15.c12_vbar;
} }
switch_mode (env, new_mode); switch_mode (env, new_mode);
env->spsr = cpsr_read(env); env->spsr = cpsr_read(env);