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ETRAX-TIMER: Untabify.

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Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
Edgar E. Iglesias 2009-05-16 01:46:26 +02:00
parent 2a9859e724
commit 84ceea5736
1 changed files with 212 additions and 212 deletions
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424
hw/etraxfs_timer.c
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@ -45,293 +45,293 @@
#define R_MASKED_INTR 0x54 #define R_MASKED_INTR 0x54
struct fs_timer_t { struct fs_timer_t {
CPUState *env; CPUState *env;
qemu_irq *irq; qemu_irq *irq;
qemu_irq *nmi; qemu_irq *nmi;
QEMUBH *bh_t0; QEMUBH *bh_t0;
QEMUBH *bh_t1; QEMUBH *bh_t1;
QEMUBH *bh_wd; QEMUBH *bh_wd;
ptimer_state *ptimer_t0; ptimer_state *ptimer_t0;
ptimer_state *ptimer_t1; ptimer_state *ptimer_t1;
ptimer_state *ptimer_wd; ptimer_state *ptimer_wd;
struct timeval last; struct timeval last;
int wd_hits; int wd_hits;
/* Control registers. */ /* Control registers. */
uint32_t rw_tmr0_div; uint32_t rw_tmr0_div;
uint32_t r_tmr0_data; uint32_t r_tmr0_data;
uint32_t rw_tmr0_ctrl; uint32_t rw_tmr0_ctrl;
uint32_t rw_tmr1_div; uint32_t rw_tmr1_div;
uint32_t r_tmr1_data; uint32_t r_tmr1_data;
uint32_t rw_tmr1_ctrl; uint32_t rw_tmr1_ctrl;
uint32_t rw_wd_ctrl; uint32_t rw_wd_ctrl;
uint32_t rw_intr_mask; uint32_t rw_intr_mask;
uint32_t rw_ack_intr; uint32_t rw_ack_intr;
uint32_t r_intr; uint32_t r_intr;
uint32_t r_masked_intr; uint32_t r_masked_intr;
}; };
static uint32_t timer_readl (void *opaque, target_phys_addr_t addr) static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
{ {
struct fs_timer_t *t = opaque; struct fs_timer_t *t = opaque;
uint32_t r = 0; uint32_t r = 0;
switch (addr) { switch (addr) {
case R_TMR0_DATA: case R_TMR0_DATA:
r = ptimer_get_count(t->ptimer_t0); r = ptimer_get_count(t->ptimer_t0);
break; break;
case R_TMR1_DATA: case R_TMR1_DATA:
r = ptimer_get_count(t->ptimer_t1); r = ptimer_get_count(t->ptimer_t1);
break; break;
case R_TIME: case R_TIME:
r = qemu_get_clock(vm_clock) / 10; r = qemu_get_clock(vm_clock) / 10;
break; break;
case RW_INTR_MASK: case RW_INTR_MASK:
r = t->rw_intr_mask; r = t->rw_intr_mask;
break; break;
case R_MASKED_INTR: case R_MASKED_INTR:
r = t->r_intr & t->rw_intr_mask; r = t->r_intr & t->rw_intr_mask;
break; break;
default: default:
D(printf ("%s %x\n", __func__, addr)); D(printf ("%s %x\n", __func__, addr));
break; break;
} }
return r; return r;
} }
#define TIMER_SLOWDOWN 1 #define TIMER_SLOWDOWN 1
static void update_ctrl(struct fs_timer_t *t, int tnum) static void update_ctrl(struct fs_timer_t *t, int tnum)
{ {
unsigned int op; unsigned int op;
unsigned int freq; unsigned int freq;
unsigned int freq_hz; unsigned int freq_hz;
unsigned int div; unsigned int div;
uint32_t ctrl; uint32_t ctrl;
ptimer_state *timer; ptimer_state *timer;
if (tnum == 0) { if (tnum == 0) {
ctrl = t->rw_tmr0_ctrl; ctrl = t->rw_tmr0_ctrl;
div = t->rw_tmr0_div; div = t->rw_tmr0_div;
timer = t->ptimer_t0; timer = t->ptimer_t0;
} else { } else {
ctrl = t->rw_tmr1_ctrl; ctrl = t->rw_tmr1_ctrl;
div = t->rw_tmr1_div; div = t->rw_tmr1_div;
timer = t->ptimer_t1; timer = t->ptimer_t1;
} }
op = ctrl & 3; op = ctrl & 3;
freq = ctrl >> 2; freq = ctrl >> 2;
freq_hz = 32000000; freq_hz = 32000000;
switch (freq) switch (freq)
{ {
case 0: case 0:
case 1: case 1:
D(printf ("extern or disabled timer clock?\n")); D(printf ("extern or disabled timer clock?\n"));
break; break;
case 4: freq_hz = 29493000; break; case 4: freq_hz = 29493000; break;
case 5: freq_hz = 32000000; break; case 5: freq_hz = 32000000; break;
case 6: freq_hz = 32768000; break; case 6: freq_hz = 32768000; break;
case 7: freq_hz = 100000000; break; case 7: freq_hz = 100000000; break;
default: default:
abort(); abort();
break; break;
} }
D(printf ("freq_hz=%d div=%d\n", freq_hz, div)); D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
div = div * TIMER_SLOWDOWN; div = div * TIMER_SLOWDOWN;
div /= 1000; div /= 1000;
freq_hz /= 1000; freq_hz /= 1000;
ptimer_set_freq(timer, freq_hz); ptimer_set_freq(timer, freq_hz);
ptimer_set_limit(timer, div, 0); ptimer_set_limit(timer, div, 0);
switch (op) switch (op)
{ {
case 0: case 0:
/* Load. */ /* Load. */
ptimer_set_limit(timer, div, 1); ptimer_set_limit(timer, div, 1);
break; break;
case 1: case 1:
/* Hold. */ /* Hold. */
ptimer_stop(timer); ptimer_stop(timer);
break; break;
case 2: case 2:
/* Run. */ /* Run. */
ptimer_run(timer, 0); ptimer_run(timer, 0);
break; break;
default: default:
abort(); abort();
break; break;
} }
} }
static void timer_update_irq(struct fs_timer_t *t) static void timer_update_irq(struct fs_timer_t *t)
{ {
t->r_intr &= ~(t->rw_ack_intr); t->r_intr &= ~(t->rw_ack_intr);
t->r_masked_intr = t->r_intr & t->rw_intr_mask; t->r_masked_intr = t->r_intr & t->rw_intr_mask;
D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr)); D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
qemu_set_irq(t->irq[0], !!t->r_masked_intr); qemu_set_irq(t->irq[0], !!t->r_masked_intr);
} }
static void timer0_hit(void *opaque) static void timer0_hit(void *opaque)
{ {
struct fs_timer_t *t = opaque; struct fs_timer_t *t = opaque;
t->r_intr |= 1; t->r_intr |= 1;
timer_update_irq(t); timer_update_irq(t);
} }
static void timer1_hit(void *opaque) static void timer1_hit(void *opaque)
{ {
struct fs_timer_t *t = opaque; struct fs_timer_t *t = opaque;
t->r_intr |= 2; t->r_intr |= 2;
timer_update_irq(t); timer_update_irq(t);
} }
static void watchdog_hit(void *opaque) static void watchdog_hit(void *opaque)
{ {
struct fs_timer_t *t = opaque; struct fs_timer_t *t = opaque;
if (t->wd_hits == 0) { if (t->wd_hits == 0) {
/* real hw gives a single tick before reseting but we are /* real hw gives a single tick before reseting but we are
a bit friendlier to compensate for our slower execution. */ a bit friendlier to compensate for our slower execution. */
ptimer_set_count(t->ptimer_wd, 10); ptimer_set_count(t->ptimer_wd, 10);
ptimer_run(t->ptimer_wd, 1); ptimer_run(t->ptimer_wd, 1);
qemu_irq_raise(t->nmi[0]); qemu_irq_raise(t->nmi[0]);
} }
else else
qemu_system_reset_request(); qemu_system_reset_request();
t->wd_hits++; t->wd_hits++;
} }
static inline void timer_watchdog_update(struct fs_timer_t *t, uint32_t value) static inline void timer_watchdog_update(struct fs_timer_t *t, uint32_t value)
{ {
unsigned int wd_en = t->rw_wd_ctrl & (1 << 8); unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
unsigned int wd_key = t->rw_wd_ctrl >> 9; unsigned int wd_key = t->rw_wd_ctrl >> 9;
unsigned int wd_cnt = t->rw_wd_ctrl & 511; unsigned int wd_cnt = t->rw_wd_ctrl & 511;
unsigned int new_key = value >> 9 & ((1 << 7) - 1); unsigned int new_key = value >> 9 & ((1 << 7) - 1);
unsigned int new_cmd = (value >> 8) & 1; unsigned int new_cmd = (value >> 8) & 1;
/* If the watchdog is enabled, they written key must match the /* If the watchdog is enabled, they written key must match the
complement of the previous. */ complement of the previous. */
wd_key = ~wd_key & ((1 << 7) - 1); wd_key = ~wd_key & ((1 << 7) - 1);
if (wd_en && wd_key != new_key) if (wd_en && wd_key != new_key)
return; return;
D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n", D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
wd_en, new_key, wd_key, new_cmd, wd_cnt)); wd_en, new_key, wd_key, new_cmd, wd_cnt));
if (t->wd_hits) if (t->wd_hits)
qemu_irq_lower(t->nmi[0]); qemu_irq_lower(t->nmi[0]);
t->wd_hits = 0; t->wd_hits = 0;
ptimer_set_freq(t->ptimer_wd, 760); ptimer_set_freq(t->ptimer_wd, 760);
if (wd_cnt == 0) if (wd_cnt == 0)
wd_cnt = 256; wd_cnt = 256;
ptimer_set_count(t->ptimer_wd, wd_cnt); ptimer_set_count(t->ptimer_wd, wd_cnt);
if (new_cmd) if (new_cmd)
ptimer_run(t->ptimer_wd, 1); ptimer_run(t->ptimer_wd, 1);
else else
ptimer_stop(t->ptimer_wd); ptimer_stop(t->ptimer_wd);
t->rw_wd_ctrl = value; t->rw_wd_ctrl = value;
} }
static void static void
timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value) timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{ {
struct fs_timer_t *t = opaque; struct fs_timer_t *t = opaque;
switch (addr) switch (addr)
{ {
case RW_TMR0_DIV: case RW_TMR0_DIV:
t->rw_tmr0_div = value; t->rw_tmr0_div = value;
break; break;
case RW_TMR0_CTRL: case RW_TMR0_CTRL:
D(printf ("RW_TMR0_CTRL=%x\n", value)); D(printf ("RW_TMR0_CTRL=%x\n", value));
t->rw_tmr0_ctrl = value; t->rw_tmr0_ctrl = value;
update_ctrl(t, 0); update_ctrl(t, 0);
break; break;
case RW_TMR1_DIV: case RW_TMR1_DIV:
t->rw_tmr1_div = value; t->rw_tmr1_div = value;
break; break;
case RW_TMR1_CTRL: case RW_TMR1_CTRL:
D(printf ("RW_TMR1_CTRL=%x\n", value)); D(printf ("RW_TMR1_CTRL=%x\n", value));
t->rw_tmr1_ctrl = value; t->rw_tmr1_ctrl = value;
update_ctrl(t, 1); update_ctrl(t, 1);
break; break;
case RW_INTR_MASK: case RW_INTR_MASK:
D(printf ("RW_INTR_MASK=%x\n", value)); D(printf ("RW_INTR_MASK=%x\n", value));
t->rw_intr_mask = value; t->rw_intr_mask = value;
timer_update_irq(t); timer_update_irq(t);
break; break;
case RW_WD_CTRL: case RW_WD_CTRL:
timer_watchdog_update(t, value); timer_watchdog_update(t, value);
break; break;
case RW_ACK_INTR: case RW_ACK_INTR:
t->rw_ack_intr = value; t->rw_ack_intr = value;
timer_update_irq(t); timer_update_irq(t);
t->rw_ack_intr = 0; t->rw_ack_intr = 0;
break; break;
default: default:
printf ("%s " TARGET_FMT_plx " %x\n", printf ("%s " TARGET_FMT_plx " %x\n",
__func__, addr, value); __func__, addr, value);
break; break;
} }
} }
static CPUReadMemoryFunc *timer_read[] = { static CPUReadMemoryFunc *timer_read[] = {
NULL, NULL, NULL, NULL,
&timer_readl, &timer_readl,
}; };
static CPUWriteMemoryFunc *timer_write[] = { static CPUWriteMemoryFunc *timer_write[] = {
NULL, NULL, NULL, NULL,
&timer_writel, &timer_writel,
}; };
static void etraxfs_timer_reset(void *opaque) static void etraxfs_timer_reset(void *opaque)
{ {
struct fs_timer_t *t = opaque; struct fs_timer_t *t = opaque;
ptimer_stop(t->ptimer_t0); ptimer_stop(t->ptimer_t0);
ptimer_stop(t->ptimer_t1); ptimer_stop(t->ptimer_t1);
ptimer_stop(t->ptimer_wd); ptimer_stop(t->ptimer_wd);
t->rw_wd_ctrl = 0; t->rw_wd_ctrl = 0;
t->r_intr = 0; t->r_intr = 0;
t->rw_intr_mask = 0; t->rw_intr_mask = 0;
qemu_irq_lower(t->irq[0]); qemu_irq_lower(t->irq[0]);
} }
void etraxfs_timer_init(CPUState *env, qemu_irq *irqs, qemu_irq *nmi, void etraxfs_timer_init(CPUState *env, qemu_irq *irqs, qemu_irq *nmi,
target_phys_addr_t base) target_phys_addr_t base)
{ {
static struct fs_timer_t *t; static struct fs_timer_t *t;
int timer_regs; int timer_regs;
t = qemu_mallocz(sizeof *t); t = qemu_mallocz(sizeof *t);
t->bh_t0 = qemu_bh_new(timer0_hit, t); t->bh_t0 = qemu_bh_new(timer0_hit, t);
t->bh_t1 = qemu_bh_new(timer1_hit, t); t->bh_t1 = qemu_bh_new(timer1_hit, t);
t->bh_wd = qemu_bh_new(watchdog_hit, t); t->bh_wd = qemu_bh_new(watchdog_hit, t);
t->ptimer_t0 = ptimer_init(t->bh_t0); t->ptimer_t0 = ptimer_init(t->bh_t0);
t->ptimer_t1 = ptimer_init(t->bh_t1); t->ptimer_t1 = ptimer_init(t->bh_t1);
t->ptimer_wd = ptimer_init(t->bh_wd); t->ptimer_wd = ptimer_init(t->bh_wd);
t->irq = irqs; t->irq = irqs;
t->nmi = nmi; t->nmi = nmi;
t->env = env; t->env = env;
timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t); timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t);
cpu_register_physical_memory (base, 0x5c, timer_regs); cpu_register_physical_memory (base, 0x5c, timer_regs);
qemu_register_reset(etraxfs_timer_reset, t); qemu_register_reset(etraxfs_timer_reset, t);
} }