proxmox-mirrors/qemu
1
0
Fork 0
mirror of https://git.proxmox.com/git/qemu synced 2025-08-06 15:24:34 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

axis_dev88: convert to memory API

Browse Source 
Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Avi Kivity 2011-11-14 11:17:21 +02:00
parent 7ef57cca57
commit 838335ecf3
1 changed files with 30 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

63
hw/axis_dev88.c
View File

@ -39,6 +39,7 @@
struct nand_state_t struct nand_state_t
{ {
DeviceState *nand; DeviceState *nand;
MemoryRegion iomem;
unsigned int rdy:1; unsigned int rdy:1;
unsigned int ale:1; unsigned int ale:1;
unsigned int cle:1; unsigned int cle:1;
@ -46,7 +47,7 @@ struct nand_state_t
}; };
static struct nand_state_t nand_state; static struct nand_state_t nand_state;
static uint32_t nand_readl (void *opaque, target_phys_addr_t addr) static uint64_t nand_read(void *opaque, target_phys_addr_t addr, unsigned size)
{ {
struct nand_state_t *s = opaque; struct nand_state_t *s = opaque;
uint32_t r; uint32_t r;
@ -61,31 +62,25 @@ static uint32_t nand_readl (void *opaque, target_phys_addr_t addr)
} }
static void static void
nand_writel (void *opaque, target_phys_addr_t addr, uint32_t value) nand_write(void *opaque, target_phys_addr_t addr, uint64_t value,
unsigned size)
{ {
struct nand_state_t *s = opaque; struct nand_state_t *s = opaque;
int rdy; int rdy;
DNAND(printf("%s addr=%x v=%x\n", __func__, addr, value)); DNAND(printf("%s addr=%x v=%x\n", __func__, addr, (unsigned)value));
nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0); nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
nand_setio(s->nand, value); nand_setio(s->nand, value);
nand_getpins(s->nand, &rdy); nand_getpins(s->nand, &rdy);
s->rdy = rdy; s->rdy = rdy;
} }
static CPUReadMemoryFunc * const nand_read[] = { static const MemoryRegionOps nand_ops = {
&nand_readl, .read = nand_read,
&nand_readl, .write = nand_write,
&nand_readl, .endianness = DEVICE_NATIVE_ENDIAN,
}; };
static CPUWriteMemoryFunc * const nand_write[] = {
&nand_writel,
&nand_writel,
&nand_writel,
};
struct tempsensor_t struct tempsensor_t
{ {
unsigned int shiftreg; unsigned int shiftreg;
@ -165,12 +160,13 @@ static void tempsensor_clkedge(struct tempsensor_t *s,
static struct gpio_state_t static struct gpio_state_t
{ {
MemoryRegion iomem;
struct nand_state_t *nand; struct nand_state_t *nand;
struct tempsensor_t tempsensor; struct tempsensor_t tempsensor;
uint32_t regs[0x5c / 4]; uint32_t regs[0x5c / 4];
} gpio_state; } gpio_state;
static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr) static uint64_t gpio_read(void *opaque, target_phys_addr_t addr, unsigned size)
{ {
struct gpio_state_t *s = opaque; struct gpio_state_t *s = opaque;
uint32_t r = 0; uint32_t r = 0;
@ -199,10 +195,11 @@ static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr)
D(printf("%s %x=%x\n", __func__, addr, r)); D(printf("%s %x=%x\n", __func__, addr, r));
} }
static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value) static void gpio_write(void *opaque, target_phys_addr_t addr, uint64_t value,
unsigned size)
{ {
struct gpio_state_t *s = opaque; struct gpio_state_t *s = opaque;
D(printf("%s %x=%x\n", __func__, addr, value)); D(printf("%s %x=%x\n", __func__, addr, (unsigned)value));
addr >>= 2; addr >>= 2;
switch (addr) switch (addr)
@ -230,14 +227,14 @@ static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
} }
} }
static CPUReadMemoryFunc * const gpio_read[] = { static const MemoryRegionOps gpio_ops = {
NULL, NULL, .read = gpio_read,
&gpio_readl, .write = gpio_write,
}; .endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
static CPUWriteMemoryFunc * const gpio_write[] = { .min_access_size = 4,
NULL, NULL, .max_access_size = 4,
&gpio_writel, },
}; };
#define INTMEM_SIZE (128 * 1024) #define INTMEM_SIZE (128 * 1024)
@ -258,8 +255,6 @@ void axisdev88_init (ram_addr_t ram_size,
void *etraxfs_dmac; void *etraxfs_dmac;
struct etraxfs_dma_client *dma_eth; struct etraxfs_dma_client *dma_eth;
int i; int i;
int nand_regs;
int gpio_regs;
MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *phys_ram = g_new(MemoryRegion, 1); MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
MemoryRegion *phys_intmem = g_new(MemoryRegion, 1); MemoryRegion *phys_intmem = g_new(MemoryRegion, 1);
@ -283,14 +278,16 @@ void axisdev88_init (ram_addr_t ram_size,
nand = drive_get(IF_MTD, 0, 0); nand = drive_get(IF_MTD, 0, 0);
nand_state.nand = nand_init(nand ? nand->bdrv : NULL, nand_state.nand = nand_init(nand ? nand->bdrv : NULL,
NAND_MFR_STMICRO, 0x39); NAND_MFR_STMICRO, 0x39);
nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state, memory_region_init_io(&nand_state.iomem, &nand_ops, &nand_state,
DEVICE_NATIVE_ENDIAN); "nand", 0x05000000);
cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs); memory_region_add_subregion(address_space_mem, 0x10000000,
&nand_state.iomem);
gpio_state.nand = &nand_state; gpio_state.nand = &nand_state;
gpio_regs = cpu_register_io_memory(gpio_read, gpio_write, &gpio_state, memory_region_init_io(&gpio_state.iomem, &gpio_ops, &gpio_state,
DEVICE_NATIVE_ENDIAN); "gpio", 0x5c);
cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs); memory_region_add_subregion(address_space_mem, 0x3001a000,
&gpio_state.iomem);
cpu_irq = cris_pic_init_cpu(env); cpu_irq = cris_pic_init_cpu(env);