proxmox-mirrors/qemu
1
0
Fork 0
mirror of https://git.proxmox.com/git/qemu synced 2025-07-05 07:34:34 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

tcg-hppa: Remove automatically implemented opcodes.

Browse Source 
Remove neg, ext8u, ext16u, as requested.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Richard Henderson 2010-04-10 22:22:28 +02:00 committed by Aurelien Jarno
parent 2d097a83e2
commit 70ec48ef55
2 changed files with 5 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
tcg/hppa/tcg-target.c
View File

@ -1431,19 +1431,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
tcg_out_ext16s(s, args[0], args[1]); tcg_out_ext16s(s, args[0], args[1]);
break; break;
/* These three correspond exactly to the fallback implementation.
But by including them we reduce the number of TCG ops that
need to be generated, and these opcodes are fairly common. */
case INDEX_op_neg_i32:
tcg_out_arith(s, args[0], TCG_REG_R0, args[1], INSN_SUB);
break;
case INDEX_op_ext8u_i32:
tcg_out_andi(s, args[0], args[1], 0xff);
break;
case INDEX_op_ext16u_i32:
tcg_out_andi(s, args[0], args[1], 0xffff);
break;
case INDEX_op_brcond_i32: case INDEX_op_brcond_i32:
tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], args[3]); tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], args[3]);
break; break;
@ -1550,13 +1537,10 @@ static const TCGTargetOpDef hppa_op_defs[] = {
{ INDEX_op_bswap16_i32, { "r", "r" } }, { INDEX_op_bswap16_i32, { "r", "r" } },
{ INDEX_op_bswap32_i32, { "r", "r" } }, { INDEX_op_bswap32_i32, { "r", "r" } },
{ INDEX_op_neg_i32, { "r", "r" } },
{ INDEX_op_not_i32, { "r", "r" } }, { INDEX_op_not_i32, { "r", "r" } },
{ INDEX_op_ext8s_i32, { "r", "r" } }, { INDEX_op_ext8s_i32, { "r", "r" } },
{ INDEX_op_ext8u_i32, { "r", "r" } },
{ INDEX_op_ext16s_i32, { "r", "r" } }, { INDEX_op_ext16s_i32, { "r", "r" } },
{ INDEX_op_ext16u_i32, { "r", "r" } },
{ INDEX_op_brcond_i32, { "rZ", "rJ" } }, { INDEX_op_brcond_i32, { "rZ", "rJ" } },
{ INDEX_op_brcond2_i32, { "rZ", "rZ", "rJ", "rJ" } }, { INDEX_op_brcond2_i32, { "rZ", "rZ", "rJ", "rJ" } },

8
tcg/hppa/tcg-target.h
View File

@ -89,15 +89,17 @@ enum {
#define TCG_TARGET_HAS_rot_i32 #define TCG_TARGET_HAS_rot_i32
#define TCG_TARGET_HAS_ext8s_i32 #define TCG_TARGET_HAS_ext8s_i32
#define TCG_TARGET_HAS_ext16s_i32 #define TCG_TARGET_HAS_ext16s_i32
#define TCG_TARGET_HAS_ext8u_i32
#define TCG_TARGET_HAS_ext16u_i32
#define TCG_TARGET_HAS_bswap16_i32 #define TCG_TARGET_HAS_bswap16_i32
#define TCG_TARGET_HAS_bswap32_i32 #define TCG_TARGET_HAS_bswap32_i32
#define TCG_TARGET_HAS_not_i32 #define TCG_TARGET_HAS_not_i32
#define TCG_TARGET_HAS_neg_i32
#define TCG_TARGET_HAS_andc_i32 #define TCG_TARGET_HAS_andc_i32
// #define TCG_TARGET_HAS_orc_i32 // #define TCG_TARGET_HAS_orc_i32
/* optional instructions automatically implemented */
#undef TCG_TARGET_HAS_neg_i32 /* sub rd, 0, rs */
#undef TCG_TARGET_HAS_ext8u_i32 /* and rd, rs, 0xff */
#undef TCG_TARGET_HAS_ext16u_i32 /* and rd, rs, 0xffff */
#define TCG_TARGET_HAS_GUEST_BASE #define TCG_TARGET_HAS_GUEST_BASE
/* Note: must be synced with dyngen-exec.h */ /* Note: must be synced with dyngen-exec.h */