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Name the magic constants, wrap long lines

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3751 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2007-12-01 14:51:23 +00:00
parent 2d8ee4e719
commit 5ad6bb97a4
2 changed files with 135 additions and 85 deletions
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188
hw/esp.c
View File

@ -32,8 +32,8 @@
//#define DEBUG_ESP //#define DEBUG_ESP
/* /*
* On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), also * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
* produced as NCR89C100. See * also produced as NCR89C100. See
* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
* and * and
* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
@ -81,12 +81,51 @@ struct ESPState {
void *dma_opaque; void *dma_opaque;
}; };
#define ESP_TCLO 0x0
#define ESP_TCMID 0x1
#define ESP_FIFO 0x2
#define ESP_CMD 0x3
#define ESP_RSTAT 0x4
#define ESP_WBUSID 0x4
#define ESP_RINTR 0x5
#define ESP_WSEL 0x5
#define ESP_RSEQ 0x6
#define ESP_WSYNTP 0x6
#define ESP_RFLAGS 0x7
#define ESP_WSYNO 0x7
#define ESP_CFG1 0x8
#define ESP_RRES1 0x9
#define ESP_WCCF 0x9
#define ESP_RRES2 0xa
#define ESP_WTEST 0xa
#define ESP_CFG2 0xb
#define ESP_CFG3 0xc
#define ESP_RES3 0xd
#define ESP_TCHI 0xe
#define ESP_RES4 0xf
#define CMD_DMA 0x80
#define CMD_CMD 0x7f
#define CMD_NOP 0x00
#define CMD_FLUSH 0x01
#define CMD_RESET 0x02
#define CMD_BUSRESET 0x03
#define CMD_TI 0x10
#define CMD_ICCS 0x11
#define CMD_MSGACC 0x12
#define CMD_SATN 0x1a
#define CMD_SELATN 0x42
#define CMD_SELATNS 0x43
#define CMD_ENSEL 0x44
#define STAT_DO 0x00 #define STAT_DO 0x00
#define STAT_DI 0x01 #define STAT_DI 0x01
#define STAT_CD 0x02 #define STAT_CD 0x02
#define STAT_ST 0x03 #define STAT_ST 0x03
#define STAT_MI 0x06 #define STAT_MI 0x06
#define STAT_MO 0x07 #define STAT_MO 0x07
#define STAT_PIO_MASK 0x06
#define STAT_TC 0x10 #define STAT_TC 0x10
#define STAT_PE 0x20 #define STAT_PE 0x20
@ -101,13 +140,19 @@ struct ESPState {
#define SEQ_0 0x0 #define SEQ_0 0x0
#define SEQ_CD 0x4 #define SEQ_CD 0x4
#define CFG1_RESREPT 0x40
#define CFG2_MASK 0x15
#define TCHI_FAS100A 0x4
static int get_cmd(ESPState *s, uint8_t *buf) static int get_cmd(ESPState *s, uint8_t *buf)
{ {
uint32_t dmalen; uint32_t dmalen;
int target; int target;
dmalen = s->rregs[0] | (s->rregs[1] << 8); dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
target = s->wregs[4] & 7; target = s->wregs[ESP_WBUSID] & 7;
DPRINTF("get_cmd: len %d target %d\n", dmalen, target); DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
if (s->dma) { if (s->dma) {
espdma_memory_read(s->dma_opaque, buf, dmalen); espdma_memory_read(s->dma_opaque, buf, dmalen);
@ -129,9 +174,9 @@ static int get_cmd(ESPState *s, uint8_t *buf)
if (target >= MAX_DISKS || !s->scsi_dev[target]) { if (target >= MAX_DISKS || !s->scsi_dev[target]) {
// No such drive // No such drive
s->rregs[4] = STAT_IN; s->rregs[ESP_RSTAT] = STAT_IN;
s->rregs[5] = INTR_DC; s->rregs[ESP_RINTR] = INTR_DC;
s->rregs[6] = SEQ_0; s->rregs[ESP_RSEQ] = SEQ_0;
qemu_irq_raise(s->irq); qemu_irq_raise(s->irq);
return 0; return 0;
} }
@ -149,19 +194,19 @@ static void do_cmd(ESPState *s, uint8_t *buf)
datalen = scsi_send_command(s->current_dev, 0, &buf[1], lun); datalen = scsi_send_command(s->current_dev, 0, &buf[1], lun);
s->ti_size = datalen; s->ti_size = datalen;
if (datalen != 0) { if (datalen != 0) {
s->rregs[4] = STAT_IN | STAT_TC; s->rregs[ESP_RSTAT] = STAT_IN | STAT_TC;
s->dma_left = 0; s->dma_left = 0;
s->dma_counter = 0; s->dma_counter = 0;
if (datalen > 0) { if (datalen > 0) {
s->rregs[4] |= STAT_DI; s->rregs[ESP_RSTAT] |= STAT_DI;
scsi_read_data(s->current_dev, 0); scsi_read_data(s->current_dev, 0);
} else { } else {
s->rregs[4] |= STAT_DO; s->rregs[ESP_RSTAT] |= STAT_DO;
scsi_write_data(s->current_dev, 0); scsi_write_data(s->current_dev, 0);
} }
} }
s->rregs[5] = INTR_BS | INTR_FC; s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
s->rregs[6] = SEQ_CD; s->rregs[ESP_RSEQ] = SEQ_CD;
qemu_irq_raise(s->irq); qemu_irq_raise(s->irq);
} }
@ -181,9 +226,9 @@ static void handle_satn_stop(ESPState *s)
if (s->cmdlen) { if (s->cmdlen) {
DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen); DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
s->do_cmd = 1; s->do_cmd = 1;
s->rregs[4] = STAT_IN | STAT_TC | STAT_CD; s->rregs[ESP_RSTAT] = STAT_IN | STAT_TC | STAT_CD;
s->rregs[5] = INTR_BS | INTR_FC; s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
s->rregs[6] = SEQ_CD; s->rregs[ESP_RSEQ] = SEQ_CD;
qemu_irq_raise(s->irq); qemu_irq_raise(s->irq);
} }
} }
@ -195,26 +240,26 @@ static void write_response(ESPState *s)
s->ti_buf[1] = 0; s->ti_buf[1] = 0;
if (s->dma) { if (s->dma) {
espdma_memory_write(s->dma_opaque, s->ti_buf, 2); espdma_memory_write(s->dma_opaque, s->ti_buf, 2);
s->rregs[4] = STAT_IN | STAT_TC | STAT_ST; s->rregs[ESP_RSTAT] = STAT_IN | STAT_TC | STAT_ST;
s->rregs[5] = INTR_BS | INTR_FC; s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
s->rregs[6] = SEQ_CD; s->rregs[ESP_RSEQ] = SEQ_CD;
} else { } else {
s->ti_size = 2; s->ti_size = 2;
s->ti_rptr = 0; s->ti_rptr = 0;
s->ti_wptr = 0; s->ti_wptr = 0;
s->rregs[7] = 2; s->rregs[ESP_RFLAGS] = 2;
} }
qemu_irq_raise(s->irq); qemu_irq_raise(s->irq);
} }
static void esp_dma_done(ESPState *s) static void esp_dma_done(ESPState *s)
{ {
s->rregs[4] |= STAT_IN | STAT_TC; s->rregs[ESP_RSTAT] |= STAT_IN | STAT_TC;
s->rregs[5] = INTR_BS; s->rregs[ESP_RINTR] = INTR_BS;
s->rregs[6] = 0; s->rregs[ESP_RSEQ] = 0;
s->rregs[7] = 0; s->rregs[ESP_RFLAGS] = 0;
s->rregs[0] = 0; s->rregs[ESP_TCLO] = 0;
s->rregs[1] = 0; s->rregs[ESP_TCMID] = 0;
qemu_irq_raise(s->irq); qemu_irq_raise(s->irq);
} }
@ -287,7 +332,7 @@ static void esp_command_complete(void *opaque, int reason, uint32_t tag,
if (arg) if (arg)
DPRINTF("Command failed\n"); DPRINTF("Command failed\n");
s->sense = arg; s->sense = arg;
s->rregs[4] = STAT_ST; s->rregs[ESP_RSTAT] = STAT_ST;
esp_dma_done(s); esp_dma_done(s);
s->current_dev = NULL; s->current_dev = NULL;
} else { } else {
@ -308,7 +353,7 @@ static void handle_ti(ESPState *s)
{ {
uint32_t dmalen, minlen; uint32_t dmalen, minlen;
dmalen = s->rregs[0] | (s->rregs[1] << 8); dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
if (dmalen==0) { if (dmalen==0) {
dmalen=0x10000; dmalen=0x10000;
} }
@ -323,7 +368,7 @@ static void handle_ti(ESPState *s)
DPRINTF("Transfer Information len %d\n", minlen); DPRINTF("Transfer Information len %d\n", minlen);
if (s->dma) { if (s->dma) {
s->dma_left = minlen; s->dma_left = minlen;
s->rregs[4] &= ~STAT_TC; s->rregs[ESP_RSTAT] &= ~STAT_TC;
esp_do_dma(s); esp_do_dma(s);
} else if (s->do_cmd) { } else if (s->do_cmd) {
DPRINTF("command len %d\n", s->cmdlen); DPRINTF("command len %d\n", s->cmdlen);
@ -341,7 +386,7 @@ static void esp_reset(void *opaque)
memset(s->rregs, 0, ESP_REGS); memset(s->rregs, 0, ESP_REGS);
memset(s->wregs, 0, ESP_REGS); memset(s->wregs, 0, ESP_REGS);
s->rregs[0x0e] = 0x4; // Indicate fas100a s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a
s->ti_size = 0; s->ti_size = 0;
s->ti_rptr = 0; s->ti_rptr = 0;
s->ti_wptr = 0; s->ti_wptr = 0;
@ -363,16 +408,15 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
saddr = (addr & ESP_MASK) >> 2; saddr = (addr & ESP_MASK) >> 2;
DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]); DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
switch (saddr) { switch (saddr) {
case 2: case ESP_FIFO:
// FIFO
if (s->ti_size > 0) { if (s->ti_size > 0) {
s->ti_size--; s->ti_size--;
if ((s->rregs[4] & 6) == 0) { if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
/* Data in/out. */ /* Data in/out. */
fprintf(stderr, "esp: PIO data read not implemented\n"); fprintf(stderr, "esp: PIO data read not implemented\n");
s->rregs[2] = 0; s->rregs[ESP_FIFO] = 0;
} else { } else {
s->rregs[2] = s->ti_buf[s->ti_rptr++]; s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
} }
qemu_irq_raise(s->irq); qemu_irq_raise(s->irq);
} }
@ -381,10 +425,9 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
s->ti_wptr = 0; s->ti_wptr = 0;
} }
break; break;
case 5: case ESP_RINTR:
// interrupt
// Clear interrupt/error status bits // Clear interrupt/error status bits
s->rregs[4] &= ~(STAT_IN | STAT_GE | STAT_PE); s->rregs[ESP_RSTAT] &= ~(STAT_IN | STAT_GE | STAT_PE);
qemu_irq_lower(s->irq); qemu_irq_lower(s->irq);
break; break;
default: default:
@ -399,17 +442,17 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
uint32_t saddr; uint32_t saddr;
saddr = (addr & ESP_MASK) >> 2; saddr = (addr & ESP_MASK) >> 2;
DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr], val); DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr],
val);
switch (saddr) { switch (saddr) {
case 0: case ESP_TCLO:
case 1: case ESP_TCMID:
s->rregs[4] &= ~STAT_TC; s->rregs[ESP_RSTAT] &= ~STAT_TC;
break; break;
case 2: case ESP_FIFO:
// FIFO
if (s->do_cmd) { if (s->do_cmd) {
s->cmdbuf[s->cmdlen++] = val & 0xff; s->cmdbuf[s->cmdlen++] = val & 0xff;
} else if ((s->rregs[4] & 6) == 0) { } else if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
uint8_t buf; uint8_t buf;
buf = val & 0xff; buf = val & 0xff;
s->ti_size--; s->ti_size--;
@ -419,63 +462,62 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
s->ti_buf[s->ti_wptr++] = val & 0xff; s->ti_buf[s->ti_wptr++] = val & 0xff;
} }
break; break;
case 3: case ESP_CMD:
s->rregs[saddr] = val; s->rregs[saddr] = val;
// Command if (val & CMD_DMA) {
if (val & 0x80) {
s->dma = 1; s->dma = 1;
/* Reload DMA counter. */ /* Reload DMA counter. */
s->rregs[0] = s->wregs[0]; s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO];
s->rregs[1] = s->wregs[1]; s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID];
} else { } else {
s->dma = 0; s->dma = 0;
} }
switch(val & 0x7f) { switch(val & CMD_CMD) {
case 0: case CMD_NOP:
DPRINTF("NOP (%2.2x)\n", val); DPRINTF("NOP (%2.2x)\n", val);
break; break;
case 1: case CMD_FLUSH:
DPRINTF("Flush FIFO (%2.2x)\n", val); DPRINTF("Flush FIFO (%2.2x)\n", val);
//s->ti_size = 0; //s->ti_size = 0;
s->rregs[5] = INTR_FC; s->rregs[ESP_RINTR] = INTR_FC;
s->rregs[6] = 0; s->rregs[ESP_RSEQ] = 0;
break; break;
case 2: case CMD_RESET:
DPRINTF("Chip reset (%2.2x)\n", val); DPRINTF("Chip reset (%2.2x)\n", val);
esp_reset(s); esp_reset(s);
break; break;
case 3: case CMD_BUSRESET:
DPRINTF("Bus reset (%2.2x)\n", val); DPRINTF("Bus reset (%2.2x)\n", val);
s->rregs[5] = INTR_RST; s->rregs[ESP_RINTR] = INTR_RST;
if (!(s->wregs[8] & 0x40)) { if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
qemu_irq_raise(s->irq); qemu_irq_raise(s->irq);
} }
break; break;
case 0x10: case CMD_TI:
handle_ti(s); handle_ti(s);
break; break;
case 0x11: case CMD_ICCS:
DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val); DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
write_response(s); write_response(s);
break; break;
case 0x12: case CMD_MSGACC:
DPRINTF("Message Accepted (%2.2x)\n", val); DPRINTF("Message Accepted (%2.2x)\n", val);
write_response(s); write_response(s);
s->rregs[5] = INTR_DC; s->rregs[ESP_RINTR] = INTR_DC;
s->rregs[6] = 0; s->rregs[ESP_RSEQ] = 0;
break; break;
case 0x1a: case CMD_SATN:
DPRINTF("Set ATN (%2.2x)\n", val); DPRINTF("Set ATN (%2.2x)\n", val);
break; break;
case 0x42: case CMD_SELATN:
DPRINTF("Set ATN (%2.2x)\n", val); DPRINTF("Set ATN (%2.2x)\n", val);
handle_satn(s); handle_satn(s);
break; break;
case 0x43: case CMD_SELATNS:
DPRINTF("Set ATN & stop (%2.2x)\n", val); DPRINTF("Set ATN & stop (%2.2x)\n", val);
handle_satn_stop(s); handle_satn_stop(s);
break; break;
case 0x44: case CMD_ENSEL:
DPRINTF("Enable selection (%2.2x)\n", val); DPRINTF("Enable selection (%2.2x)\n", val);
break; break;
default: default:
@ -483,17 +525,17 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
break; break;
} }
break; break;
case 4 ... 7: case ESP_WBUSID ... ESP_WSYNO:
break; break;
case 8: case ESP_CFG1:
s->rregs[saddr] = val; s->rregs[saddr] = val;
break; break;
case 9 ... 10: case ESP_WCCF ... ESP_WTEST:
break; break;
case 11: case ESP_CFG2:
s->rregs[saddr] = val & 0x15; s->rregs[saddr] = val & CFG2_MASK;
break; break;
case 12 ... 15: case ESP_CFG3 ... ESP_RES4:
s->rregs[saddr] = val; s->rregs[saddr] = val;
break; break;
default: default:

32
hw/iommu.c
View File

@ -61,12 +61,16 @@ do { printf("IOMMU: " fmt , ##args); } while (0)
#define IOMMU_AFSR (0x1000 >> 2) #define IOMMU_AFSR (0x1000 >> 2)
#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */ #define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after transaction */ #define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after
#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than 12.8 us. */ transaction */
#define IOMMU_AFSR_BE 0x10000000 /* Write access received error acknowledge */ #define IOMMU_AFSR_TO 0x20000000 /* Write access took more than
12.8 us. */
#define IOMMU_AFSR_BE 0x10000000 /* Write access received error
acknowledge */
#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */ #define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */ #define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
#define IOMMU_AFSR_RESV 0x00f00000 /* Reserved, forced to 0x8 by hardware */ #define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by
hardware */
#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */ #define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */ #define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */ #define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
@ -77,7 +81,8 @@ do { printf("IOMMU: " fmt , ##args); } while (0)
#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */ #define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */ #define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */ #define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when bypass enabled */ #define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when
bypass enabled */
#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */ #define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */ #define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
@ -91,7 +96,8 @@ do { printf("IOMMU: " fmt , ##args); } while (0)
/* The format of an iopte in the page tables */ /* The format of an iopte in the page tables */
#define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */ #define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */
#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */ #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or
Viking/MXCC) */
#define IOPTE_WRITE 0x00000004 /* Writeable */ #define IOPTE_WRITE 0x00000004 /* Writeable */
#define IOPTE_VALID 0x00000002 /* IOPTE is valid */ #define IOPTE_VALID 0x00000002 /* IOPTE is valid */
#define IOPTE_WAZ 0x00000001 /* Write as zeros */ #define IOPTE_WAZ 0x00000001 /* Write as zeros */
@ -122,7 +128,8 @@ static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
return 0; return 0;
} }
static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) static void iommu_mem_writew(void *opaque, target_phys_addr_t addr,
uint32_t val)
{ {
IOMMUState *s = opaque; IOMMUState *s = opaque;
target_phys_addr_t saddr; target_phys_addr_t saddr;
@ -235,10 +242,11 @@ static target_phys_addr_t iommu_translate_pa(IOMMUState *s,
return pa; return pa;
} }
static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr, int is_write) static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
int is_write)
{ {
DPRINTF("bad addr " TARGET_FMT_plx "\n", addr); DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | (8 << 20) | s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
IOMMU_AFSR_FAV; IOMMU_AFSR_FAV;
if (!is_write) if (!is_write)
s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD; s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
@ -311,7 +319,7 @@ static void iommu_reset(void *opaque)
s->iostart = 0; s->iostart = 0;
s->regs[IOMMU_CTRL] = s->version; s->regs[IOMMU_CTRL] = s->version;
s->regs[IOMMU_ARBEN] = IOMMU_MID; s->regs[IOMMU_ARBEN] = IOMMU_MID;
s->regs[IOMMU_AFSR] = 0x00800000; s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
} }
void *iommu_init(target_phys_addr_t addr, uint32_t version) void *iommu_init(target_phys_addr_t addr, uint32_t version)
@ -326,7 +334,8 @@ void *iommu_init(target_phys_addr_t addr, uint32_t version)
s->addr = addr; s->addr = addr;
s->version = version; s->version = version;
iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s); iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read,
iommu_mem_write, s);
cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory); cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
register_savevm("iommu", addr, 2, iommu_save, iommu_load, s); register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
@ -334,4 +343,3 @@ void *iommu_init(target_phys_addr_t addr, uint32_t version)
iommu_reset(s); iommu_reset(s);
return s; return s;
} }