proxmox-mirrors/qemu
1
0
Fork 0
mirror of https://git.proxmox.com/git/qemu synced 2025-08-14 15:36:25 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

target-arm: fix LDMIA bug on page boundary

Browse Source 
target-arm: fix LDMIA bug on page boundary

When consecutive memory locations are on page boundary, a base register may be
loaded before page fault occurs. After page fault handling, it losts the memory
location information. To solve this problem, loading a base register has to put back.

Signed-off-by: Yuyeon Oh <yuyeon.oh@samsung.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
YuYeon Oh 2011-04-25 01:23:58 +00:00 committed by Aurelien Jarno
parent 47f7be394a
commit 5856d44eb5
1 changed files with 9 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
target-arm/translate.c
View File

@ -8016,7 +8016,8 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
} }
} }
} else { } else {
int i; int i, loaded_base = 0;
TCGv loaded_var;
/* Load/store multiple. */ /* Load/store multiple. */
addr = load_reg(s, rn); addr = load_reg(s, rn);
offset = 0; offset = 0;
@ -8028,6 +8029,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
tcg_gen_addi_i32(addr, addr, -offset); tcg_gen_addi_i32(addr, addr, -offset);
} }
TCGV_UNUSED(loaded_var);
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {
if ((insn & (1 << i)) == 0) if ((insn & (1 << i)) == 0)
continue; continue;
@ -8036,6 +8038,9 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
tmp = gen_ld32(addr, IS_USER(s)); tmp = gen_ld32(addr, IS_USER(s));
if (i == 15) { if (i == 15) {
gen_bx(s, tmp); gen_bx(s, tmp);
} else if (i == rn) {
loaded_var = tmp;
loaded_base = 1;
} else { } else {
store_reg(s, i, tmp); store_reg(s, i, tmp);
} }
@ -8046,6 +8051,9 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
} }
tcg_gen_addi_i32(addr, addr, 4); tcg_gen_addi_i32(addr, addr, 4);
} }
if (loaded_base) {
store_reg(s, rn, loaded_var);
}
if (insn & (1 << 21)) { if (insn & (1 << 21)) {
/* Base register writeback. */ /* Base register writeback. */
if (insn & (1 << 24)) { if (insn & (1 << 24)) {