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PPC: E500: Add ESR bit definitions

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The BookE spec specifies a number of ESR bits. Add defines for them
so we can use them later on.

Reported-by: Jason Wessel <jason.wessel@windriver.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
Alexander Graf 2011-08-23 06:55:42 +02:00 committed by Edgar E. Iglesias
parent 710ffe6048
commit 542df9bfb7
2 changed files with 18 additions and 3 deletions
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17
target-ppc/cpu.h
View File

@ -516,7 +516,22 @@ struct ppc_slb_t {
#endif #endif
/* Exception state register bits definition */ /* Exception state register bits definition */
#define ESR_ST 23 /* Exception was caused by a store type access. */ #define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
#define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
#define ESR_PTR (1 << (63 - 38)) /* Trap */
#define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */
#define ESR_ST (1 << (63 - 40)) /* Store Operation */
#define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */
#define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */
#define ESR_BO (1 << (63 - 46)) /* Byte Ordering */
#define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */
#define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */
#define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */
#define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */
#define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */
#define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */
#define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
#define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
enum { enum {
POWERPC_FLAG_NONE = 0x00000000, POWERPC_FLAG_NONE = 0x00000000,

4
target-ppc/helper.c
View File

@ -1837,7 +1837,7 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
env->exception_index = POWERPC_EXCP_DTLB; env->exception_index = POWERPC_EXCP_DTLB;
env->error_code = 0; env->error_code = 0;
env->spr[SPR_BOOKE_DEAR] = address; env->spr[SPR_BOOKE_DEAR] = address;
env->spr[SPR_BOOKE_ESR] = rw ? 1 << ESR_ST : 0; env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0;
return -1; return -1;
case POWERPC_MMU_REAL: case POWERPC_MMU_REAL:
cpu_abort(env, "PowerPC in real mode should never raise " cpu_abort(env, "PowerPC in real mode should never raise "
@ -1861,7 +1861,7 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
} else if ((env->mmu_model == POWERPC_MMU_BOOKE) || } else if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
(env->mmu_model == POWERPC_MMU_BOOKE206)) { (env->mmu_model == POWERPC_MMU_BOOKE206)) {
env->spr[SPR_BOOKE_DEAR] = address; env->spr[SPR_BOOKE_DEAR] = address;
env->spr[SPR_BOOKE_ESR] = rw ? 1 << ESR_ST : 0; env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0;
} else { } else {
env->spr[SPR_DAR] = address; env->spr[SPR_DAR] = address;
if (rw == 1) { if (rw == 1) {