proxmox-mirrors/qemu
1
0
Fork 0
mirror of https://git.proxmox.com/git/qemu synced 2025-08-16 08:13:06 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

target-mips: fix host CPU consumption when guest is idle

Browse Source 
When the CPU is in wait state, do not wake-up if an interrupt can't be
taken. This avoid host CPU running at 100% if a device (e.g. timer) has
an interrupt line left enabled.

Also factorize code to check if interrupts are enabled in
cpu_mips_hw_interrupts_pending().

Based on a patch from Edgar E. Iglesias <edgar.iglesias@gmail.com>

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
Aurelien Jarno 2010-12-25 22:56:32 +01:00
parent 6c33286ad3
commit 4cdc1cd137
3 changed files with 24 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
cpu-exec.c
View File

@ -454,11 +454,7 @@ int cpu_exec(CPUState *env1)
} }
#elif defined(TARGET_MIPS) #elif defined(TARGET_MIPS)
if ((interrupt_request & CPU_INTERRUPT_HARD) && if ((interrupt_request & CPU_INTERRUPT_HARD) &&
cpu_mips_hw_interrupts_pending(env) && cpu_mips_hw_interrupts_pending(env)) {
(env->CP0_Status & (1 << CP0St_IE)) &&
!(env->CP0_Status & (1 << CP0St_EXL)) &&
!(env->CP0_Status & (1 << CP0St_ERL)) &&
!(env->hflags & MIPS_HFLAG_DM)) {
/* Raise it */ /* Raise it */
env->exception_index = EXCP_EXT_INTERRUPT; env->exception_index = EXCP_EXT_INTERRUPT;
env->error_code = 0; env->error_code = 0;

8
target-mips/cpu.h
View File

@ -532,6 +532,14 @@ static inline int cpu_mips_hw_interrupts_pending(CPUState *env)
int32_t status; int32_t status;
int r; int r;
if (!(env->CP0_Status & (1 << CP0St_IE)) ||
(env->CP0_Status & (1 << CP0St_EXL)) ||
(env->CP0_Status & (1 << CP0St_ERL)) ||
(env->hflags & MIPS_HFLAG_DM)) {
/* Interrupts are disabled */
return 0;
}
pending = env->CP0_Cause & CP0Ca_IP_mask; pending = env->CP0_Cause & CP0Ca_IP_mask;
status = env->CP0_Status & CP0Ca_IP_mask; status = env->CP0_Status & CP0Ca_IP_mask;

18
target-mips/exec.h
View File

@ -19,10 +19,22 @@ register struct CPUMIPSState *env asm(AREG0);
static inline int cpu_has_work(CPUState *env) static inline int cpu_has_work(CPUState *env)
{ {
return (env->interrupt_request & int has_work = 0;
(CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER));
}
/* It is implementation dependent if non-enabled interrupts
wake-up the CPU, however most of the implementations only
check for interrupts that can be taken. */
if ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
cpu_mips_hw_interrupts_pending(env)) {
has_work = 1;
}
if (env->interrupt_request & CPU_INTERRUPT_TIMER) {
has_work = 1;
}
return has_work;
}
static inline int cpu_halted(CPUState *env) static inline int cpu_halted(CPUState *env)
{ {