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https://git.proxmox.com/git/qemu
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2104 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
parent
8ccad811e6
commit
35b961cf8d
86
hw/lance.c
86
hw/lance.c
@ -145,9 +145,9 @@ struct lance_init_block {
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struct lance_rx_desc brx_ring[RX_RING_SIZE];
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struct lance_tx_desc btx_ring[TX_RING_SIZE];
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char tx_buf [TX_RING_SIZE][TX_BUFF_SIZE];
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char tx_buf[TX_RING_SIZE][TX_BUFF_SIZE];
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char pad[2]; /* align rx_buf for copy_and_sum(). */
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char rx_buf [RX_RING_SIZE][RX_BUFF_SIZE];
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char rx_buf[RX_RING_SIZE][RX_BUFF_SIZE];
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};
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#define LEDMA_REGS 4
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@ -192,13 +192,14 @@ static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr)
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DPRINTF("read areg = %4.4x\n", s->addr);
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return s->addr;
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default:
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DPRINTF("read unknown(%d)\n", saddr>>1);
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DPRINTF("read unknown(%d)\n", saddr >> 1);
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break;
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}
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return 0;
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}
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static void lance_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
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static void lance_mem_writew(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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LANCEState *s = opaque;
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uint32_t saddr;
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@ -208,7 +209,7 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val
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switch (saddr >> 1) {
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case LE_RDP:
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DPRINTF("write dreg[%d] = %4.4x\n", s->addr, val);
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switch(s->addr) {
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switch (s->addr) {
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case LE_CSR0:
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if (val & LE_C0_STOP) {
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s->regs[LE_CSR0] = LE_C0_STOP;
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@ -235,8 +236,7 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val
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if (val & LE_C0_INIT) {
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reg |= LE_C0_IDON | LE_C0_INIT;
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reg &= ~LE_C0_STOP;
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}
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else if (val & LE_C0_STRT) {
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} else if (val & LE_C0_STRT) {
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reg |= LE_C0_STRT | LE_C0_RXON | LE_C0_TXON;
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reg &= ~LE_C0_STOP;
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}
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@ -262,7 +262,7 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val
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s->addr = val;
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break;
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default:
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DPRINTF("write unknown(%d) = %4.4x\n", saddr>>1, val);
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DPRINTF("write unknown(%d) = %4.4x\n", saddr >> 1, val);
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break;
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}
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lance_send(s);
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@ -288,7 +288,7 @@ static int lance_can_receive(void *opaque)
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return 1;
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}
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static void lance_receive(void *opaque, const uint8_t *buf, int size)
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static void lance_receive(void *opaque, const uint8_t * buf, int size)
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{
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LANCEState *s = opaque;
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uint32_t dmaptr = s->leptr + s->ledmaregs[3];
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@ -304,16 +304,21 @@ static void lance_receive(void *opaque, const uint8_t *buf, int size)
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ib = (void *) iommu_translate(dmaptr);
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old_rxptr = s->rxptr;
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for (i = s->rxptr; i != ((old_rxptr - 1) & RX_RING_MOD_MASK); i = (i + 1) & RX_RING_MOD_MASK) {
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cpu_physical_memory_read((uint32_t)&ib->brx_ring[i].rmd1_bits, (void *) &temp8, 1);
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for (i = s->rxptr; i != ((old_rxptr - 1) & RX_RING_MOD_MASK);
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i = (i + 1) & RX_RING_MOD_MASK) {
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cpu_physical_memory_read((uint32_t) & ib->brx_ring[i].rmd1_bits,
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(void *) &temp8, 1);
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if (temp8 == (LE_R1_OWN)) {
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s->rxptr = (s->rxptr + 1) & RX_RING_MOD_MASK;
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temp16 = size + 4;
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bswap16s(&temp16);
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cpu_physical_memory_write((uint32_t)&ib->brx_ring[i].mblength, (void *) &temp16, 2);
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cpu_physical_memory_write((uint32_t)&ib->rx_buf[i], buf, size);
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cpu_physical_memory_write((uint32_t) & ib->brx_ring[i].
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mblength, (void *) &temp16, 2);
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cpu_physical_memory_write((uint32_t) & ib->rx_buf[i], buf,
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size);
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temp8 = LE_R1_POK;
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cpu_physical_memory_write((uint32_t)&ib->brx_ring[i].rmd1_bits, (void *) &temp8, 1);
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cpu_physical_memory_write((uint32_t) & ib->brx_ring[i].
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rmd1_bits, (void *) &temp8, 1);
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s->regs[LE_CSR0] |= LE_C0_RINT | LE_C0_INTR;
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if (s->regs[LE_CSR0] & LE_C0_INEA)
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pic_set_irq(s->irq, 1);
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@ -339,19 +344,25 @@ static void lance_send(void *opaque)
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ib = (void *) iommu_translate(dmaptr);
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DPRINTF("sending packet? (dmaptr %8.8x) (ib %p) (btx_ring %p)\n", dmaptr, ib, &ib->btx_ring);
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DPRINTF("sending packet? (dmaptr %8.8x) (ib %p) (btx_ring %p)\n",
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dmaptr, ib, &ib->btx_ring);
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old_txptr = s->txptr;
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for (i = s->txptr; i != ((old_txptr - 1) & TX_RING_MOD_MASK); i = (i + 1) & TX_RING_MOD_MASK) {
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cpu_physical_memory_read((uint32_t)&ib->btx_ring[i].tmd1_bits, (void *) &temp8, 1);
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if (temp8 == (LE_T1_POK|LE_T1_OWN)) {
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cpu_physical_memory_read((uint32_t)&ib->btx_ring[i].length, (void *) &temp16, 2);
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for (i = s->txptr; i != ((old_txptr - 1) & TX_RING_MOD_MASK);
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i = (i + 1) & TX_RING_MOD_MASK) {
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cpu_physical_memory_read((uint32_t) & ib->btx_ring[i].tmd1_bits,
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(void *) &temp8, 1);
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if (temp8 == (LE_T1_POK | LE_T1_OWN)) {
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cpu_physical_memory_read((uint32_t) & ib->btx_ring[i].length,
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(void *) &temp16, 2);
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bswap16s(&temp16);
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temp16 = (~temp16) + 1;
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cpu_physical_memory_read((uint32_t)&ib->tx_buf[i], pkt_buf, temp16);
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cpu_physical_memory_read((uint32_t) & ib->tx_buf[i], pkt_buf,
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temp16);
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DPRINTF("sending packet, len %d\n", temp16);
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qemu_send_packet(s->vc, pkt_buf, temp16);
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temp8 = LE_T1_POK;
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cpu_physical_memory_write((uint32_t)&ib->btx_ring[i].tmd1_bits, (void *) &temp8, 1);
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cpu_physical_memory_write((uint32_t) & ib->btx_ring[i].
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tmd1_bits, (void *) &temp8, 1);
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s->txptr = (s->txptr + 1) & TX_RING_MOD_MASK;
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s->regs[LE_CSR0] |= LE_C0_TINT | LE_C0_INTR;
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}
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@ -369,7 +380,8 @@ static uint32_t ledma_mem_readl(void *opaque, target_phys_addr_t addr)
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return s->ledmaregs[saddr];
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}
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static void ledma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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static void ledma_mem_writel(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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LANCEState *s = opaque;
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uint32_t saddr;
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@ -390,22 +402,22 @@ static CPUWriteMemoryFunc *ledma_mem_write[3] = {
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ledma_mem_writel,
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};
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static void lance_save(QEMUFile *f, void *opaque)
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static void lance_save(QEMUFile * f, void *opaque)
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{
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LANCEState *s = opaque;
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int i;
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qemu_put_be32s(f, &s->leptr);
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qemu_put_be16s(f, &s->addr);
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for (i = 0; i < LE_NREGS; i ++)
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for (i = 0; i < LE_NREGS; i++)
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qemu_put_be16s(f, &s->regs[i]);
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qemu_put_buffer(f, s->phys, 6);
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qemu_put_be32s(f, &s->irq);
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for (i = 0; i < LEDMA_REGS; i ++)
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for (i = 0; i < LEDMA_REGS; i++)
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qemu_put_be32s(f, &s->ledmaregs[i]);
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}
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static int lance_load(QEMUFile *f, void *opaque, int version_id)
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static int lance_load(QEMUFile * f, void *opaque, int version_id)
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{
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LANCEState *s = opaque;
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int i;
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@ -415,16 +427,16 @@ static int lance_load(QEMUFile *f, void *opaque, int version_id)
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qemu_get_be32s(f, &s->leptr);
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qemu_get_be16s(f, &s->addr);
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for (i = 0; i < LE_NREGS; i ++)
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for (i = 0; i < LE_NREGS; i++)
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qemu_get_be16s(f, &s->regs[i]);
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qemu_get_buffer(f, s->phys, 6);
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qemu_get_be32s(f, &s->irq);
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for (i = 0; i < LEDMA_REGS; i ++)
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for (i = 0; i < LEDMA_REGS; i++)
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qemu_get_be32s(f, &s->ledmaregs[i]);
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return 0;
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}
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void lance_init(NICInfo *nd, int irq, uint32_t leaddr, uint32_t ledaddr)
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void lance_init(NICInfo * nd, int irq, uint32_t leaddr, uint32_t ledaddr)
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{
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LANCEState *s;
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int lance_io_memory, ledma_io_memory;
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@ -435,28 +447,28 @@ void lance_init(NICInfo *nd, int irq, uint32_t leaddr, uint32_t ledaddr)
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s->irq = irq;
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lance_io_memory = cpu_register_io_memory(0, lance_mem_read, lance_mem_write, s);
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lance_io_memory =
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cpu_register_io_memory(0, lance_mem_read, lance_mem_write, s);
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cpu_register_physical_memory(leaddr, 4, lance_io_memory);
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ledma_io_memory = cpu_register_io_memory(0, ledma_mem_read, ledma_mem_write, s);
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ledma_io_memory =
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cpu_register_io_memory(0, ledma_mem_read, ledma_mem_write, s);
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cpu_register_physical_memory(ledaddr, 16, ledma_io_memory);
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memcpy(s->macaddr, nd->macaddr, 6);
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lance_reset(s);
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s->vc = qemu_new_vlan_client(nd->vlan, lance_receive, lance_can_receive, s);
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s->vc =
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qemu_new_vlan_client(nd->vlan, lance_receive, lance_can_receive,
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s);
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snprintf(s->vc->info_str, sizeof(s->vc->info_str),
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"lance macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
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s->macaddr[0],
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s->macaddr[1],
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s->macaddr[2],
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s->macaddr[3],
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s->macaddr[4],
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s->macaddr[5]);
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s->macaddr[2], s->macaddr[3], s->macaddr[4], s->macaddr[5]);
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register_savevm("lance", leaddr, 1, lance_save, lance_load, s);
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qemu_register_reset(lance_reset, s);
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}
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