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target-openrisc: Move cpu_gdb_{read,write}_register()

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Reviewed-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Andreas Färber 2013-07-07 12:40:38 +02:00
parent 814ac26c2d
commit 30028739eb
2 changed files with 78 additions and 56 deletions
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57
gdbstub.c
View File

@ -554,63 +554,8 @@ static int put_packet(GDBState *s, const char *buf)
#elif defined(TARGET_OPENRISC) #elif defined(TARGET_OPENRISC)
static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n) #include "target-openrisc/gdbstub.c"
{
if (n < 32) {
GET_REG32(env->gpr[n]);
} else {
switch (n) {
case 32: /* PPC */
GET_REG32(env->ppc);
case 33: /* NPC */
GET_REG32(env->npc);
case 34: /* SR */
GET_REG32(env->sr);
default:
break;
}
}
return 0;
}
static int cpu_gdb_write_register(CPUOpenRISCState *env,
uint8_t *mem_buf, int n)
{
OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
CPUClass *cc = CPU_GET_CLASS(cpu);
uint32_t tmp;
if (n > cc->gdb_num_core_regs) {
return 0;
}
tmp = ldl_p(mem_buf);
if (n < 32) {
env->gpr[n] = tmp;
} else {
switch (n) {
case 32: /* PPC */
env->ppc = tmp;
break;
case 33: /* NPC */
env->npc = tmp;
break;
case 34: /* SR */
env->sr = tmp;
break;
default:
break;
}
}
return 4;
}
#elif defined (TARGET_SH4) #elif defined (TARGET_SH4)
/* Hint: Use "set architecture sh4" in GDB to see fpu registers */ /* Hint: Use "set architecture sh4" in GDB to see fpu registers */

77
target-openrisc/gdbstub.c Normal file
View File

@ -0,0 +1,77 @@
/*
* OpenRISC gdb server stub
*
* Copyright (c) 2003-2005 Fabrice Bellard
* Copyright (c) 2013 SUSE LINUX Products GmbH
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
GET_REG32(env->gpr[n]);
} else {
switch (n) {
case 32: /* PPC */
GET_REG32(env->ppc);
case 33: /* NPC */
GET_REG32(env->npc);
case 34: /* SR */
GET_REG32(env->sr);
default:
break;
}
}
return 0;
}
static int cpu_gdb_write_register(CPUOpenRISCState *env,
uint8_t *mem_buf, int n)
{
OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
CPUClass *cc = CPU_GET_CLASS(cpu);
uint32_t tmp;
if (n > cc->gdb_num_core_regs) {
return 0;
}
tmp = ldl_p(mem_buf);
if (n < 32) {
env->gpr[n] = tmp;
} else {
switch (n) {
case 32: /* PPC */
env->ppc = tmp;
break;
case 33: /* NPC */
env->npc = tmp;
break;
case 34: /* SR */
env->sr = tmp;
break;
default:
break;
}
}
return 4;
}