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Make SYNCI_Step and CCRes CPU-specific.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2651 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-04-11 20:34:23 +00:00
parent b48cfdffd9
commit 2f6445458e
2 changed files with 16 additions and 3 deletions
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3
target-mips/translate.c
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@ -5435,9 +5435,6 @@ void cpu_reset (CPUMIPSState *env)
env->hflags |= MIPS_HFLAG_UM; env->hflags |= MIPS_HFLAG_UM;
env->user_mode_only = 1; env->user_mode_only = 1;
#endif #endif
/* XXX some guesswork here, values are CPU specific */
env->SYNCI_Step = 16;
env->CCRes = 2;
} }
#include "translate_init.c" #include "translate_init.c"

16
target-mips/translate_init.c
View File

@ -67,6 +67,8 @@ struct mips_def_t {
int32_t CP0_Config3; int32_t CP0_Config3;
int32_t CP0_Config6; int32_t CP0_Config6;
int32_t CP0_Config7; int32_t CP0_Config7;
int32_t SYNCI_Step;
int32_t CCRes;
int32_t CP1_fcr0; int32_t CP1_fcr0;
}; };
@ -82,6 +84,8 @@ static mips_def_t mips_defs[] =
.CP0_Config1 = MIPS_CONFIG1, .CP0_Config1 = MIPS_CONFIG1,
.CP0_Config2 = MIPS_CONFIG2, .CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3, .CP0_Config3 = MIPS_CONFIG3,
.SYNCI_Step = 32,
.CCRes = 2,
.CP1_fcr0 = MIPS_FCR0, .CP1_fcr0 = MIPS_FCR0,
}, },
{ {
@ -91,6 +95,8 @@ static mips_def_t mips_defs[] =
.CP0_Config1 = MIPS_CONFIG1, .CP0_Config1 = MIPS_CONFIG1,
.CP0_Config2 = MIPS_CONFIG2, .CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3, .CP0_Config3 = MIPS_CONFIG3,
.SYNCI_Step = 32,
.CCRes = 2,
.CP1_fcr0 = MIPS_FCR0, .CP1_fcr0 = MIPS_FCR0,
}, },
{ {
@ -100,6 +106,8 @@ static mips_def_t mips_defs[] =
.CP0_Config1 = MIPS_CONFIG1, .CP0_Config1 = MIPS_CONFIG1,
.CP0_Config2 = MIPS_CONFIG2, .CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3, .CP0_Config3 = MIPS_CONFIG3,
.SYNCI_Step = 32,
.CCRes = 2,
.CP1_fcr0 = MIPS_FCR0, .CP1_fcr0 = MIPS_FCR0,
}, },
{ {
@ -109,6 +117,8 @@ static mips_def_t mips_defs[] =
.CP0_Config1 = MIPS_CONFIG1, .CP0_Config1 = MIPS_CONFIG1,
.CP0_Config2 = MIPS_CONFIG2, .CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3, .CP0_Config3 = MIPS_CONFIG3,
.SYNCI_Step = 32,
.CCRes = 2,
.CP1_fcr0 = MIPS_FCR0, .CP1_fcr0 = MIPS_FCR0,
}, },
{ {
@ -118,6 +128,8 @@ static mips_def_t mips_defs[] =
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP), .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),
.CP0_Config2 = MIPS_CONFIG2, .CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3, .CP0_Config3 = MIPS_CONFIG3,
.SYNCI_Step = 32,
.CCRes = 2,
.CP1_fcr0 = MIPS_FCR0, .CP1_fcr0 = MIPS_FCR0,
}, },
#else #else
@ -128,6 +140,8 @@ static mips_def_t mips_defs[] =
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP), .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),
.CP0_Config2 = MIPS_CONFIG2, .CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3, .CP0_Config3 = MIPS_CONFIG3,
.SYNCI_Step = 16,
.CCRes = 2,
.CP1_fcr0 = MIPS_FCR0, .CP1_fcr0 = MIPS_FCR0,
}, },
#endif #endif
@ -175,6 +189,8 @@ int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
env->CP0_Config3 = def->CP0_Config3; env->CP0_Config3 = def->CP0_Config3;
env->CP0_Config6 = def->CP0_Config6; env->CP0_Config6 = def->CP0_Config6;
env->CP0_Config7 = def->CP0_Config7; env->CP0_Config7 = def->CP0_Config7;
env->SYNCI_Step = def->SYNCI_Step;
env->CCRes = def->CCRes;
env->fcr0 = def->CP1_fcr0; env->fcr0 = def->CP1_fcr0;
return 0; return 0;
} }