proxmox-mirrors/qemu
1
0
Fork 0
mirror of https://git.proxmox.com/git/qemu synced 2025-07-09 19:08:05 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

isa memory remapping support (aka PPC PREP VGA support)

Browse Source 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@773 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard 2004-04-28 22:26:05 +00:00
parent 8e9c4afe70
commit 26aa7d72cc
4 changed files with 38 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
hw/ppc_prep.c
View File

@ -896,7 +896,7 @@ void PPC_end_init (void)
VGA_init(); VGA_init();
} }
/* PC hardware initialisation */ /* PowerPC PREP hardware initialisation */
void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device, void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device,
DisplayState *ds, const char **fd_filename, int snapshot, DisplayState *ds, const char **fd_filename, int snapshot,
const char *kernel_filename, const char *kernel_cmdline, const char *kernel_filename, const char *kernel_cmdline,
@ -911,6 +911,8 @@ void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device,
/* allocate RAM */ /* allocate RAM */
cpu_register_physical_memory(0, ram_size, 0); cpu_register_physical_memory(0, ram_size, 0);
isa_mem_base = 0xc0000000;
if (linux_boot) { if (linux_boot) {
/* now we can load the kernel */ /* now we can load the kernel */
ret = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); ret = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);

29
hw/vga.c
View File

@ -549,7 +549,7 @@ static void vbe_ioport_write(void *opaque, uint32_t addr, uint32_t val)
case VBE_DISPI_INDEX_BANK: case VBE_DISPI_INDEX_BANK:
val &= s->vbe_bank_mask; val &= s->vbe_bank_mask;
s->vbe_regs[s->vbe_index] = val; s->vbe_regs[s->vbe_index] = val;
s->bank_offset = (val << 16) - 0xa0000; s->bank_offset = (val << 16);
break; break;
case VBE_DISPI_INDEX_ENABLE: case VBE_DISPI_INDEX_ENABLE:
if (val & VBE_DISPI_ENABLED) { if (val & VBE_DISPI_ENABLED) {
@ -603,7 +603,7 @@ static void vbe_ioport_write(void *opaque, uint32_t addr, uint32_t val)
s->vbe_regs[s->vbe_index] = val; s->vbe_regs[s->vbe_index] = val;
} else { } else {
/* XXX: the bios should do that */ /* XXX: the bios should do that */
s->bank_offset = -0xa0000; s->bank_offset = 0;
} }
break; break;
case VBE_DISPI_INDEX_VIRT_WIDTH: case VBE_DISPI_INDEX_VIRT_WIDTH:
@ -656,23 +656,23 @@ static uint32_t vga_mem_readb(target_phys_addr_t addr)
/* convert to VGA memory offset */ /* convert to VGA memory offset */
memory_map_mode = (s->gr[6] >> 2) & 3; memory_map_mode = (s->gr[6] >> 2) & 3;
addr &= 0x1ffff;
switch(memory_map_mode) { switch(memory_map_mode) {
case 0: case 0:
addr -= 0xa0000;
break; break;
case 1: case 1:
if (addr >= 0xb0000) if (addr >= 0x10000)
return 0xff; return 0xff;
addr += s->bank_offset; addr += s->bank_offset;
break; break;
case 2: case 2:
addr -= 0xb0000; addr -= 0x10000;
if (addr >= 0x8000) if (addr >= 0x8000)
return 0xff; return 0xff;
break; break;
default: default:
case 3: case 3:
addr -= 0xb8000; addr -= 0x18000;
if (addr >= 0x8000) if (addr >= 0x8000)
return 0xff; return 0xff;
break; break;
@ -734,23 +734,23 @@ static void vga_mem_writeb(target_phys_addr_t addr, uint32_t val)
#endif #endif
/* convert to VGA memory offset */ /* convert to VGA memory offset */
memory_map_mode = (s->gr[6] >> 2) & 3; memory_map_mode = (s->gr[6] >> 2) & 3;
addr &= 0x1ffff;
switch(memory_map_mode) { switch(memory_map_mode) {
case 0: case 0:
addr -= 0xa0000;
break; break;
case 1: case 1:
if (addr >= 0xb0000) if (addr >= 0x10000)
return; return;
addr += s->bank_offset; addr += s->bank_offset;
break; break;
case 2: case 2:
addr -= 0xb0000; addr -= 0x10000;
if (addr >= 0x8000) if (addr >= 0x8000)
return; return;
break; break;
default: default:
case 3: case 3:
addr -= 0xb8000; addr -= 0x18000;
if (addr >= 0x8000) if (addr >= 0x8000)
return; return;
break; break;
@ -1758,7 +1758,7 @@ int vga_initialize(DisplayState *ds, uint8_t *vga_ram_base,
register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s); register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s); register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
register_ioport_read(0x3da, 1, 1, vga_ioport_read, s); register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
s->bank_offset = -0xa0000; s->bank_offset = 0;
#ifdef CONFIG_BOCHS_VBE #ifdef CONFIG_BOCHS_VBE
s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0; s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
@ -1771,15 +1771,14 @@ int vga_initialize(DisplayState *ds, uint8_t *vga_ram_base,
#endif #endif
vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write); vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write);
#if defined (TARGET_I386) cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
cpu_register_physical_memory(0x000a0000, 0x20000, vga_io_memory); vga_io_memory);
#ifdef CONFIG_BOCHS_VBE #ifdef CONFIG_BOCHS_VBE
#if defined (TARGET_I386)
/* XXX: use optimized standard vga accesses */ /* XXX: use optimized standard vga accesses */
cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS, cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
vga_ram_size, vga_ram_offset); vga_ram_size, vga_ram_offset);
#endif #endif
#elif defined (TARGET_PPC)
cpu_register_physical_memory(0xf00a0000, 0x20000, vga_io_memory);
#endif #endif
return 0; return 0;
} }

4
vl.c
View File

@ -114,7 +114,9 @@ int vm_running;
int audio_enabled = 0; int audio_enabled = 0;
/***********************************************************/ /***********************************************************/
/* x86 io ports */ /* x86 ISA bus support */
target_phys_addr_t isa_mem_base = 0;
uint32_t default_ioport_readb(void *opaque, uint32_t address) uint32_t default_ioport_readb(void *opaque, uint32_t address)
{ {

25
vl.h
View File

@ -144,13 +144,6 @@ static inline uint16_t cpu_to_le16(uint16_t v)
/* vl.c */ /* vl.c */
extern int reset_requested; extern int reset_requested;
typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
int register_ioport_read(int start, int length, int size,
IOPortReadFunc *func, void *opaque);
int register_ioport_write(int start, int length, int size,
IOPortWriteFunc *func, void *opaque);
uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c); uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
void hw_error(const char *fmt, ...); void hw_error(const char *fmt, ...);
@ -348,6 +341,18 @@ void bdrv_set_change_cb(BlockDriverState *bs,
void bdrv_info(void); void bdrv_info(void);
BlockDriverState *bdrv_find(const char *name); BlockDriverState *bdrv_find(const char *name);
/* ISA bus */
extern target_phys_addr_t isa_mem_base;
typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
int register_ioport_read(int start, int length, int size,
IOPortReadFunc *func, void *opaque);
int register_ioport_write(int start, int length, int size,
IOPortWriteFunc *func, void *opaque);
/* vga.c */ /* vga.c */
#define VGA_RAM_SIZE (4096 * 1024) #define VGA_RAM_SIZE (4096 * 1024)
@ -503,6 +508,12 @@ void pc_init(int ram_size, int vga_ram_size, int boot_device,
const char *kernel_filename, const char *kernel_cmdline, const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename); const char *initrd_filename);
/* ppc.c */
void ppc_init (int ram_size, int vga_ram_size, int boot_device,
DisplayState *ds, const char **fd_filename, int snapshot,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename);
/* monitor.c */ /* monitor.c */
void monitor_init(void); void monitor_init(void);
void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2))); void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));