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tcg-sparc: Mask shift immediates to avoid illegal insns.

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The xtensa-test image generates a sra_i32 with count 0x40.
Whether this is accident of tcg constant propagation or
originating directly from the instruction stream is immaterial.

Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2012-03-25 21:36:28 +02:00
parent 4c3204cb12
commit 1fd9594665
1 changed files with 12 additions and 6 deletions
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18
tcg/sparc/tcg-target.c
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@ -1154,13 +1154,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
goto gen_arith; goto gen_arith;
case INDEX_op_shl_i32: case INDEX_op_shl_i32:
c = SHIFT_SLL; c = SHIFT_SLL;
goto gen_arith; do_shift32:
/* Limit immediate shift count lest we create an illegal insn. */
tcg_out_arithc(s, args[0], args[1], args[2] & 31, const_args[2], c);
break;
case INDEX_op_shr_i32: case INDEX_op_shr_i32:
c = SHIFT_SRL; c = SHIFT_SRL;
goto gen_arith; goto do_shift32;
case INDEX_op_sar_i32: case INDEX_op_sar_i32:
c = SHIFT_SRA; c = SHIFT_SRA;
goto gen_arith; goto do_shift32;
case INDEX_op_mul_i32: case INDEX_op_mul_i32:
c = ARITH_UMUL; c = ARITH_UMUL;
goto gen_arith; goto gen_arith;
@ -1281,13 +1284,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
break; break;
case INDEX_op_shl_i64: case INDEX_op_shl_i64:
c = SHIFT_SLLX; c = SHIFT_SLLX;
goto gen_arith; do_shift64:
/* Limit immediate shift count lest we create an illegal insn. */
tcg_out_arithc(s, args[0], args[1], args[2] & 63, const_args[2], c);
break;
case INDEX_op_shr_i64: case INDEX_op_shr_i64:
c = SHIFT_SRLX; c = SHIFT_SRLX;
goto gen_arith; goto do_shift64;
case INDEX_op_sar_i64: case INDEX_op_sar_i64:
c = SHIFT_SRAX; c = SHIFT_SRAX;
goto gen_arith; goto do_shift64;
case INDEX_op_mul_i64: case INDEX_op_mul_i64:
c = ARITH_MULX; c = ARITH_MULX;
goto gen_arith; goto gen_arith;