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Convert io_mem_watch to be a MemoryRegion
Signed-off-by: Avi Kivity <avi@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
parent
de712f9469
commit
1ec9b909ff
73
exec.c
73
exec.c
@ -212,7 +212,7 @@ CPUWriteMemoryFunc *_io_mem_write[IO_MEM_NB_ENTRIES][4];
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CPUReadMemoryFunc *_io_mem_read[IO_MEM_NB_ENTRIES][4];
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CPUReadMemoryFunc *_io_mem_read[IO_MEM_NB_ENTRIES][4];
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void *io_mem_opaque[IO_MEM_NB_ENTRIES];
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void *io_mem_opaque[IO_MEM_NB_ENTRIES];
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static char io_mem_used[IO_MEM_NB_ENTRIES];
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static char io_mem_used[IO_MEM_NB_ENTRIES];
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static int io_mem_watch;
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static MemoryRegion io_mem_watch;
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#endif
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#endif
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/* log support */
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/* log support */
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@ -2158,7 +2158,7 @@ void tlb_set_page(CPUState *env, target_ulong vaddr,
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if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) {
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if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) {
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/* Avoid trapping reads of pages with a write breakpoint. */
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/* Avoid trapping reads of pages with a write breakpoint. */
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if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
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if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
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iotlb = io_mem_watch + paddr;
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iotlb = io_mem_watch.ram_addr + paddr;
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address |= TLB_MMIO;
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address |= TLB_MMIO;
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break;
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break;
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}
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}
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@ -3260,55 +3260,34 @@ static void check_watchpoint(int offset, int len_mask, int flags)
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/* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
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/* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
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so these check for a hit then pass through to the normal out-of-line
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so these check for a hit then pass through to the normal out-of-line
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phys routines. */
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phys routines. */
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static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr)
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static uint64_t watch_mem_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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{
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check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ);
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check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ);
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return ldub_phys(addr);
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switch (size) {
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case 1: return ldub_phys(addr);
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case 2: return lduw_phys(addr);
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case 4: return ldl_phys(addr);
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default: abort();
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}
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}
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}
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static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr)
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static void watch_mem_write(void *opaque, target_phys_addr_t addr,
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uint64_t val, unsigned size)
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{
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{
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check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ);
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check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_WRITE);
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return lduw_phys(addr);
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switch (size) {
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case 1: stb_phys(addr, val);
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case 2: stw_phys(addr, val);
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case 4: stl_phys(addr, val);
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default: abort();
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}
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}
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}
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static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr)
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static const MemoryRegionOps watch_mem_ops = {
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{
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.read = watch_mem_read,
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check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ);
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.write = watch_mem_write,
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return ldl_phys(addr);
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.endianness = DEVICE_NATIVE_ENDIAN,
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}
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static void watch_mem_writeb(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE);
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stb_phys(addr, val);
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}
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static void watch_mem_writew(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE);
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stw_phys(addr, val);
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}
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static void watch_mem_writel(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE);
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stl_phys(addr, val);
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}
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static CPUReadMemoryFunc * const watch_mem_read[3] = {
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watch_mem_readb,
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watch_mem_readw,
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watch_mem_readl,
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};
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static CPUWriteMemoryFunc * const watch_mem_write[3] = {
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watch_mem_writeb,
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watch_mem_writew,
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watch_mem_writel,
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};
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};
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static uint64_t subpage_read(void *opaque, target_phys_addr_t addr,
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static uint64_t subpage_read(void *opaque, target_phys_addr_t addr,
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@ -3515,8 +3494,8 @@ static void io_mem_init(void)
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for (i=0; i<5; i++)
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for (i=0; i<5; i++)
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io_mem_used[i] = 1;
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io_mem_used[i] = 1;
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io_mem_watch = cpu_register_io_memory(watch_mem_read,
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memory_region_init_io(&io_mem_watch, &watch_mem_ops, NULL,
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watch_mem_write, NULL);
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"watch", UINT64_MAX);
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}
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}
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static void memory_map_init(void)
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static void memory_map_init(void)
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