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Fix erraneous fallthrough in MIPS trap implementation, thanks Atsushi Nemoto.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2247 c046a42c-6fe2-441c-8c8c-71466251a162
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ths 2006-12-16 16:45:18 +00:00
parent e4630047e1
commit 179e32bbcc
1 changed files with 1 additions and 0 deletions
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target-mips/translate.c
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@ -1276,6 +1276,7 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
GEN_LOAD_REG_TN(T1, rt); GEN_LOAD_REG_TN(T1, rt);
cond = 1; cond = 1;
} }
break;
case OPC_TEQI: case OPC_TEQI:
case OPC_TGEI: case OPC_TGEI:
case OPC_TGEIU: case OPC_TGEIU: