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PPC: Qdev'ify e500 pci
The e500 PCI controller isn't qdev'ified yet. This leads to severe issues when running with -drive. To be able to use a virtio disk with an e500 VM, let's convert the PCI controller over to qdev. Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
parent
fc87e18530
commit
13b7fdeffa
132
hw/ppce500_pci.c
132
hw/ppce500_pci.c
@ -73,11 +73,11 @@ struct pci_inbound {
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};
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};
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struct PPCE500PCIState {
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struct PPCE500PCIState {
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PCIHostState pci_state;
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struct pci_outbound pob[PPCE500_PCI_NR_POBS];
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struct pci_outbound pob[PPCE500_PCI_NR_POBS];
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struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
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struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
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uint32_t gasket_time;
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uint32_t gasket_time;
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PCIHostState pci_state;
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uint64_t base_addr;
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PCIDevice *pci_dev;
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};
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};
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typedef struct PPCE500PCIState PPCE500PCIState;
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typedef struct PPCE500PCIState PPCE500PCIState;
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@ -221,7 +221,7 @@ static void ppce500_pci_save(QEMUFile *f, void *opaque)
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PPCE500PCIState *controller = opaque;
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PPCE500PCIState *controller = opaque;
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int i;
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int i;
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pci_device_save(controller->pci_dev, f);
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/* pci_device_save(controller->pci_dev, f); */
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for (i = 0; i < PPCE500_PCI_NR_POBS; i++) {
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for (i = 0; i < PPCE500_PCI_NR_POBS; i++) {
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qemu_put_be32s(f, &controller->pob[i].potar);
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qemu_put_be32s(f, &controller->pob[i].potar);
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@ -247,7 +247,7 @@ static int ppce500_pci_load(QEMUFile *f, void *opaque, int version_id)
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if (version_id != 1)
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if (version_id != 1)
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return -EINVAL;
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return -EINVAL;
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pci_device_load(controller->pci_dev, f);
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/* pci_device_load(controller->pci_dev, f); */
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for (i = 0; i < PPCE500_PCI_NR_POBS; i++) {
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for (i = 0; i < PPCE500_PCI_NR_POBS; i++) {
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qemu_get_be32s(f, &controller->pob[i].potar);
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qemu_get_be32s(f, &controller->pob[i].potar);
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@ -269,55 +269,95 @@ static int ppce500_pci_load(QEMUFile *f, void *opaque, int version_id)
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PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers)
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PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers)
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{
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{
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PPCE500PCIState *controller;
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DeviceState *dev;
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PCIBus *b;
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PCIHostState *h;
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PPCE500PCIState *s;
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PCIDevice *d;
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PCIDevice *d;
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int index;
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static int ppce500_pci_id;
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static int ppce500_pci_id;
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controller = qemu_mallocz(sizeof(PPCE500PCIState));
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dev = qdev_create(NULL, "e500-pcihost");
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h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
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s = DO_UPCAST(PPCE500PCIState, pci_state, h);
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controller->pci_state.bus = pci_register_bus(NULL, "pci",
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qdev_prop_set_uint64(dev, "base_addr", registers);
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mpc85xx_pci_set_irq,
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b = pci_register_bus(&s->pci_state.busdev.qdev, NULL, mpc85xx_pci_set_irq,
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mpc85xx_pci_map_irq,
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mpc85xx_pci_map_irq, pci_irqs, PCI_DEVFN(0x11, 0), 4);
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pci_irqs, PCI_DEVFN(0x11, 0),
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4);
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d = pci_register_device(controller->pci_state.bus,
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"host bridge", sizeof(PCIDevice),
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0, NULL, NULL);
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pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_FREESCALE);
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s->pci_state.bus = b;
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pci_config_set_device_id(d->config, PCI_DEVICE_ID_MPC8533E);
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qdev_init_nofail(dev);
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pci_config_set_class(d->config, PCI_CLASS_PROCESSOR_POWERPC);
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d = pci_create_simple(b, 0, "e500-host-bridge");
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controller->pci_dev = d;
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/* CFGADDR */
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index = pci_host_conf_register_mmio(&controller->pci_state, 0);
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if (index < 0)
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goto free;
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cpu_register_physical_memory(registers + PCIE500_CFGADDR, 4, index);
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/* CFGDATA */
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index = pci_host_data_register_mmio(&controller->pci_state, 0);
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if (index < 0)
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goto free;
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cpu_register_physical_memory(registers + PCIE500_CFGDATA, 4, index);
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index = cpu_register_io_memory(e500_pci_reg_read,
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e500_pci_reg_write, controller);
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if (index < 0)
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goto free;
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cpu_register_physical_memory(registers + PCIE500_REG_BASE,
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PCIE500_REG_SIZE, index);
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/* XXX load/save code not tested. */
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/* XXX load/save code not tested. */
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register_savevm(&d->qdev, "ppce500_pci", ppce500_pci_id++,
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register_savevm(&d->qdev, "ppce500_pci", ppce500_pci_id++,
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1, ppce500_pci_save, ppce500_pci_load, controller);
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1, ppce500_pci_save, ppce500_pci_load, s);
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return controller->pci_state.bus;
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return b;
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free:
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printf("%s error\n", __func__);
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qemu_free(controller);
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return NULL;
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}
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}
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static int e500_pcihost_initfn(SysBusDevice *dev)
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{
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PCIHostState *h;
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PPCE500PCIState *s;
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target_phys_addr_t registers;
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int index;
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h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
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s = DO_UPCAST(PPCE500PCIState, pci_state, h);
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registers = (target_phys_addr_t)s->base_addr;
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/* CFGADDR */
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index = pci_host_conf_register_mmio(&s->pci_state, 0);
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if (index < 0)
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return -1;
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cpu_register_physical_memory(registers + PCIE500_CFGADDR, 4, index);
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/* CFGDATA */
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index = pci_host_data_register_mmio(&s->pci_state, 0);
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if (index < 0)
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return -1;
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cpu_register_physical_memory(registers + PCIE500_CFGDATA, 4, index);
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index = cpu_register_io_memory(e500_pci_reg_read,
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e500_pci_reg_write, s);
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if (index < 0)
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return -1;
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cpu_register_physical_memory(registers + PCIE500_REG_BASE,
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PCIE500_REG_SIZE, index);
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return 0;
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}
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static int e500_host_bridge_initfn(PCIDevice *dev)
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{
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pci_config_set_vendor_id(dev->config, PCI_VENDOR_ID_FREESCALE);
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pci_config_set_device_id(dev->config, PCI_DEVICE_ID_MPC8533E);
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pci_config_set_class(dev->config, PCI_CLASS_PROCESSOR_POWERPC);
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return 0;
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}
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static PCIDeviceInfo e500_host_bridge_info = {
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.qdev.name = "e500-host-bridge",
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.qdev.desc = "Host bridge",
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.qdev.size = sizeof(PCIDevice),
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.qdev.no_user = 1,
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.init = e500_host_bridge_initfn,
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};
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static SysBusDeviceInfo e500_pcihost_info = {
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.init = e500_pcihost_initfn,
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.qdev.name = "e500-pcihost",
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.qdev.size = sizeof(PPCE500PCIState),
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.qdev.no_user = 1,
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT64("base_addr", PPCE500PCIState, base_addr, 0),
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DEFINE_PROP_END_OF_LIST(),
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}
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};
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static void e500_pci_register(void)
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{
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sysbus_register_withprop(&e500_pcihost_info);
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pci_qdev_register(&e500_host_bridge_info);
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}
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device_init(e500_pci_register);
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