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tcg: Change tcg_qemu_tb_exec return to uintptr_t

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Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2013-08-20 14:35:34 -07:00
parent b93949ef6a
commit 04d5a1da70
5 changed files with 6 additions and 7 deletions
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2
cpu-exec.c
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@ -53,7 +53,7 @@ void cpu_resume_from_signal(CPUArchState *env, void *puc)
static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr) static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr)
{ {
CPUArchState *env = cpu->env_ptr; CPUArchState *env = cpu->env_ptr;
tcg_target_ulong next_tb = tcg_qemu_tb_exec(env, tb_ptr); uintptr_t next_tb = tcg_qemu_tb_exec(env, tb_ptr);
if ((next_tb & TB_EXIT_MASK) > TB_EXIT_IDX1) { if ((next_tb & TB_EXIT_MASK) > TB_EXIT_IDX1) {
/* We didn't start executing this TB (eg because the instruction /* We didn't start executing this TB (eg because the instruction
* counter hit zero); we must restore the guest PC to the address * counter hit zero); we must restore the guest PC to the address

2
tcg/ppc/tcg-target.h
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@ -102,7 +102,7 @@ typedef enum {
#define TCG_AREG0 TCG_REG_R27 #define TCG_AREG0 TCG_REG_R27
#define tcg_qemu_tb_exec(env, tb_ptr) \ #define tcg_qemu_tb_exec(env, tb_ptr) \
((long __attribute__ ((longcall)) \ ((uintptr_t __attribute__ ((longcall)) \
(*)(void *, void *))tcg_ctx.code_gen_prologue)(env, tb_ptr) (*)(void *, void *))tcg_ctx.code_gen_prologue)(env, tb_ptr)
#endif #endif

3
tcg/tcg.h
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@ -733,8 +733,7 @@ TCGv_i64 tcg_const_local_i64(int64_t val);
#if !defined(tcg_qemu_tb_exec) #if !defined(tcg_qemu_tb_exec)
# define tcg_qemu_tb_exec(env, tb_ptr) \ # define tcg_qemu_tb_exec(env, tb_ptr) \
((tcg_target_ulong (*)(void *, void *))tcg_ctx.code_gen_prologue)(env, \ ((uintptr_t (*)(void *, void *))tcg_ctx.code_gen_prologue)(env, tb_ptr)
tb_ptr)
#endif #endif
void tcg_register_jit(void *buf, size_t buf_size); void tcg_register_jit(void *buf, size_t buf_size);

2
tcg/tci/tcg-target.h
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@ -169,7 +169,7 @@ typedef enum {
void tci_disas(uint8_t opc); void tci_disas(uint8_t opc);
tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr); uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
#define tcg_qemu_tb_exec tcg_qemu_tb_exec #define tcg_qemu_tb_exec tcg_qemu_tb_exec
static inline void flush_icache_range(uintptr_t start, uintptr_t stop) static inline void flush_icache_range(uintptr_t start, uintptr_t stop)

4
tci.c
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@ -434,11 +434,11 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
} }
/* Interpret pseudo code in tb. */ /* Interpret pseudo code in tb. */
tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
{ {
long tcg_temps[CPU_TEMP_BUF_NLONGS]; long tcg_temps[CPU_TEMP_BUF_NLONGS];
uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS);
tcg_target_ulong next_tb = 0; uintptr_t next_tb = 0;
tci_reg[TCG_AREG0] = (tcg_target_ulong)env; tci_reg[TCG_AREG0] = (tcg_target_ulong)env;
tci_reg[TCG_REG_CALL_STACK] = sp_value; tci_reg[TCG_REG_CALL_STACK] = sp_value;