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https://git.proxmox.com/git/pve-qemu
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5d3fc48e11
In particular, the i386 patches fix an issue that was newly introduced in 7.2.10 and the LSI patches improve the reentrancy fix. The others also sounded relevant and nice to have. Signed-off-by: Fiona Ebner <f.ebner@proxmox.com>
131 lines
4.8 KiB
Diff
131 lines
4.8 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Paolo Bonzini <pbonzini@redhat.com>
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Date: Wed, 10 Apr 2024 08:43:50 +0300
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Subject: [PATCH] target/i386: use separate MMU indexes for 32-bit accesses
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Accesses from a 32-bit environment (32-bit code segment for instruction
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accesses, EFER.LMA==0 for processor accesses) have to mask away the
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upper 32 bits of the address. While a bit wasteful, the easiest way
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to do so is to use separate MMU indexes. These days, QEMU anyway is
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compiled with a fixed value for NB_MMU_MODES. Split MMU_USER_IDX,
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MMU_KSMAP_IDX and MMU_KNOSMAP_IDX in two.
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 90f641531c782c873a05895f411c05fbbbef3c49)
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Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
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(Mjt: move changes for x86_cpu_mmu_index() to cpu_mmu_index() due to missing
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v8.2.0-1030-gace0c5fe5950 "target/i386: Populate CPUClass.mmu_index"
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Increase NB_MMU_MODES from 5 to 8 in target/i386/cpu-param.h due to missing
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v7.2.0-2640-gffd824f3f32d "include/exec: Set default NB_MMU_MODES to 16"
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v7.2.0-2647-g6787318a5d86 "target/i386: Remove NB_MMU_MODES define"
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which relaxed upper limit of MMU index for i386, since this commit starts
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using MMU_NESTED_IDX=7.
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Thanks Zhao Liu and Paolo Bonzini for the analisys and suggestions.
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)
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---
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target/i386/cpu-param.h | 2 +-
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target/i386/cpu.h | 44 ++++++++++++++++++++--------
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target/i386/tcg/sysemu/excp_helper.c | 3 +-
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3 files changed, 34 insertions(+), 15 deletions(-)
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diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h
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index f579b16bd2..e21e472e1e 100644
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--- a/target/i386/cpu-param.h
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+++ b/target/i386/cpu-param.h
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@@ -23,7 +23,7 @@
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# define TARGET_VIRT_ADDR_SPACE_BITS 32
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#endif
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#define TARGET_PAGE_BITS 12
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-#define NB_MMU_MODES 5
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+#define NB_MMU_MODES 8
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#ifndef CONFIG_USER_ONLY
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# define TARGET_TB_PCREL 1
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index f175e18768..73eee08f3f 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -2182,27 +2182,42 @@ uint64_t cpu_get_tsc(CPUX86State *env);
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#define cpu_list x86_cpu_list
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/* MMU modes definitions */
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-#define MMU_KSMAP_IDX 0
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-#define MMU_USER_IDX 1
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-#define MMU_KNOSMAP_IDX 2
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-#define MMU_NESTED_IDX 3
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-#define MMU_PHYS_IDX 4
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+#define MMU_KSMAP64_IDX 0
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+#define MMU_KSMAP32_IDX 1
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+#define MMU_USER64_IDX 2
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+#define MMU_USER32_IDX 3
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+#define MMU_KNOSMAP64_IDX 4
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+#define MMU_KNOSMAP32_IDX 5
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+#define MMU_PHYS_IDX 6
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+#define MMU_NESTED_IDX 7
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+
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+#ifdef CONFIG_USER_ONLY
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+#ifdef TARGET_X86_64
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+#define MMU_USER_IDX MMU_USER64_IDX
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+#else
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+#define MMU_USER_IDX MMU_USER32_IDX
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+#endif
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+#endif
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static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
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{
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- return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
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- (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
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- ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
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+ int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 1 : 0;
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+ int mmu_index_base =
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+ (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER64_IDX :
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+ !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX :
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+ (env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX;
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+
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+ return mmu_index_base + mmu_index_32;
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}
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static inline bool is_mmu_index_smap(int mmu_index)
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{
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- return mmu_index == MMU_KSMAP_IDX;
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+ return (mmu_index & ~1) == MMU_KSMAP64_IDX;
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}
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static inline bool is_mmu_index_user(int mmu_index)
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{
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- return mmu_index == MMU_USER_IDX;
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+ return (mmu_index & ~1) == MMU_USER64_IDX;
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}
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static inline bool is_mmu_index_32(int mmu_index)
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@@ -2213,9 +2228,12 @@ static inline bool is_mmu_index_32(int mmu_index)
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static inline int cpu_mmu_index_kernel(CPUX86State *env)
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{
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- return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX :
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- ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK))
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- ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
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+ int mmu_index_32 = (env->hflags & HF_LMA_MASK) ? 1 : 0;
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+ int mmu_index_base =
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+ !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX :
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+ ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX;
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+
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+ return mmu_index_base + mmu_index_32;
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}
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#define CC_DST (env->cc_dst)
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diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c
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index 553a60d976..5f13252d68 100644
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--- a/target/i386/tcg/sysemu/excp_helper.c
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+++ b/target/i386/tcg/sysemu/excp_helper.c
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@@ -541,7 +541,8 @@ static bool get_physical_address(CPUX86State *env, vaddr addr,
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if (likely(use_stage2)) {
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in.cr3 = env->nested_cr3;
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in.pg_mode = env->nested_pg_mode;
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- in.mmu_idx = MMU_USER_IDX;
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+ in.mmu_idx =
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+ env->nested_pg_mode & PG_MODE_LMA ? MMU_USER64_IDX : MMU_USER32_IDX;
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in.ptw_idx = MMU_PHYS_IDX;
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if (!mmu_translate(env, &in, out, err)) {
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