mirror of
https://git.proxmox.com/git/pve-qemu
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5d3fc48e11
In particular, the i386 patches fix an issue that was newly introduced in 7.2.10 and the LSI patches improve the reentrancy fix. The others also sounded relevant and nice to have. Signed-off-by: Fiona Ebner <f.ebner@proxmox.com>
200 lines
6.0 KiB
Diff
200 lines
6.0 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Richard Henderson <richard.henderson@linaro.org>
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Date: Wed, 10 Apr 2024 08:43:26 +0300
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Subject: [PATCH] target/arm: Fix SME full tile indexing
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For the outer product set of insns, which take an entire matrix
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tile as output, the argument is not a combined tile+column.
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Therefore using get_tile_rowcol was incorrect, as we extracted
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the tile number from itself.
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The test case relies only on assembler support for SME, since
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no release of GCC recognizes -march=armv9-a+sme yet.
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Cc: qemu-stable@nongnu.org
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Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1620
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20230622151201.1578522-5-richard.henderson@linaro.org
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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[PMM: dropped now-unneeded changes to sysregs CFLAGS]
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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(cherry picked from commit 1f51573f7925b80e79a29f87c7d9d6ead60960c0)
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Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
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---
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target/arm/translate-sme.c | 24 ++++++---
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tests/tcg/aarch64/Makefile.target | 7 ++-
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tests/tcg/aarch64/sme-outprod1.c | 83 +++++++++++++++++++++++++++++++
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3 files changed, 107 insertions(+), 7 deletions(-)
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create mode 100644 tests/tcg/aarch64/sme-outprod1.c
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diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
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index 7b87a9df63..65f8495bdd 100644
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--- a/target/arm/translate-sme.c
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+++ b/target/arm/translate-sme.c
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@@ -103,6 +103,21 @@ static TCGv_ptr get_tile_rowcol(DisasContext *s, int esz, int rs,
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return addr;
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}
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+/*
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+ * Resolve tile.size[0] to a host pointer.
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+ * Used by e.g. outer product insns where we require the entire tile.
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+ */
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+static TCGv_ptr get_tile(DisasContext *s, int esz, int tile)
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+{
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+ TCGv_ptr addr = tcg_temp_new_ptr();
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+ int offset;
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+
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+ offset = tile * sizeof(ARMVectorReg) + offsetof(CPUARMState, zarray);
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+
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+ tcg_gen_addi_ptr(addr, cpu_env, offset);
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+ return addr;
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+}
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+
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static bool trans_ZERO(DisasContext *s, arg_ZERO *a)
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{
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if (!dc_isar_feature(aa64_sme, s)) {
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@@ -279,8 +294,7 @@ static bool do_adda(DisasContext *s, arg_adda *a, MemOp esz,
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return true;
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}
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- /* Sum XZR+zad to find ZAd. */
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- za = get_tile_rowcol(s, esz, 31, a->zad, false);
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+ za = get_tile(s, esz, a->zad);
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zn = vec_full_reg_ptr(s, a->zn);
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pn = pred_full_reg_ptr(s, a->pn);
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pm = pred_full_reg_ptr(s, a->pm);
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@@ -310,8 +324,7 @@ static bool do_outprod(DisasContext *s, arg_op *a, MemOp esz,
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return true;
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}
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- /* Sum XZR+zad to find ZAd. */
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- za = get_tile_rowcol(s, esz, 31, a->zad, false);
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+ za = get_tile(s, esz, a->zad);
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zn = vec_full_reg_ptr(s, a->zn);
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zm = vec_full_reg_ptr(s, a->zm);
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pn = pred_full_reg_ptr(s, a->pn);
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@@ -337,8 +350,7 @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz,
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return true;
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}
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- /* Sum XZR+zad to find ZAd. */
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- za = get_tile_rowcol(s, esz, 31, a->zad, false);
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+ za = get_tile(s, esz, a->zad);
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zn = vec_full_reg_ptr(s, a->zn);
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zm = vec_full_reg_ptr(s, a->zm);
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pn = pred_full_reg_ptr(s, a->pn);
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diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
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index 118d069073..5e4ea7c998 100644
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--- a/tests/tcg/aarch64/Makefile.target
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+++ b/tests/tcg/aarch64/Makefile.target
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@@ -24,7 +24,7 @@ config-cc.mak: Makefile
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$(call cc-option,-march=armv8.3-a, CROSS_CC_HAS_ARMV8_3); \
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$(call cc-option,-mbranch-protection=standard, CROSS_CC_HAS_ARMV8_BTI); \
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$(call cc-option,-march=armv8.5-a+memtag, CROSS_CC_HAS_ARMV8_MTE); \
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- $(call cc-option,-march=armv9-a+sme, CROSS_CC_HAS_ARMV9_SME)) 3> config-cc.mak
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+ $(call cc-option,-Wa$(COMMA)-march=armv9-a+sme, CROSS_AS_HAS_ARMV9_SME)) 3> config-cc.mak
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-include config-cc.mak
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# Pauth Tests
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@@ -51,6 +51,11 @@ AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-5 mte-6 mte-7
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mte-%: CFLAGS += -march=armv8.5-a+memtag
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endif
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+# SME Tests
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+ifneq ($(CROSS_AS_HAS_ARMV9_SME),)
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+AARCH64_TESTS += sme-outprod1
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+endif
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+
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# System Registers Tests
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AARCH64_TESTS += sysregs
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diff --git a/tests/tcg/aarch64/sme-outprod1.c b/tests/tcg/aarch64/sme-outprod1.c
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new file mode 100644
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index 0000000000..6e5972d75e
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--- /dev/null
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+++ b/tests/tcg/aarch64/sme-outprod1.c
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@@ -0,0 +1,83 @@
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+/*
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+ * SME outer product, 1 x 1.
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+ * SPDX-License-Identifier: GPL-2.0-or-later
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+ */
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+
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+#include <stdio.h>
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+
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+extern void foo(float *dst);
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+
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+asm(
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+" .arch_extension sme\n"
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+" .type foo, @function\n"
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+"foo:\n"
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+" stp x29, x30, [sp, -80]!\n"
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+" mov x29, sp\n"
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+" stp d8, d9, [sp, 16]\n"
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+" stp d10, d11, [sp, 32]\n"
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+" stp d12, d13, [sp, 48]\n"
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+" stp d14, d15, [sp, 64]\n"
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+" smstart\n"
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+" ptrue p0.s, vl4\n"
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+" fmov z0.s, #1.0\n"
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+/*
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+ * An outer product of a vector of 1.0 by itself should be a matrix of 1.0.
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+ * Note that we are using tile 1 here (za1.s) rather than tile 0.
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+ */
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+" zero {za}\n"
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+" fmopa za1.s, p0/m, p0/m, z0.s, z0.s\n"
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+/*
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+ * Read the first 4x4 sub-matrix of elements from tile 1:
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+ * Note that za1h should be interchangable here.
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+ */
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+" mov w12, #0\n"
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+" mova z0.s, p0/m, za1v.s[w12, #0]\n"
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+" mova z1.s, p0/m, za1v.s[w12, #1]\n"
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+" mova z2.s, p0/m, za1v.s[w12, #2]\n"
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+" mova z3.s, p0/m, za1v.s[w12, #3]\n"
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+/*
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+ * And store them to the input pointer (dst in the C code):
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+ */
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+" st1w {z0.s}, p0, [x0]\n"
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+" add x0, x0, #16\n"
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+" st1w {z1.s}, p0, [x0]\n"
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+" add x0, x0, #16\n"
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+" st1w {z2.s}, p0, [x0]\n"
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+" add x0, x0, #16\n"
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+" st1w {z3.s}, p0, [x0]\n"
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+" smstop\n"
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+" ldp d8, d9, [sp, 16]\n"
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+" ldp d10, d11, [sp, 32]\n"
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+" ldp d12, d13, [sp, 48]\n"
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+" ldp d14, d15, [sp, 64]\n"
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+" ldp x29, x30, [sp], 80\n"
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+" ret\n"
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+" .size foo, . - foo"
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+);
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+
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+int main()
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+{
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+ float dst[16];
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+ int i, j;
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+
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+ foo(dst);
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+
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+ for (i = 0; i < 16; i++) {
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+ if (dst[i] != 1.0f) {
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+ break;
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+ }
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+ }
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+
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+ if (i == 16) {
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+ return 0; /* success */
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+ }
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+
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+ /* failure */
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+ for (i = 0; i < 4; ++i) {
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+ for (j = 0; j < 4; ++j) {
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+ printf("%f ", (double)dst[i * 4 + j]);
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+ }
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+ printf("\n");
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+ }
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+ return 1;
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+}
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