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5d3fc48e11
In particular, the i386 patches fix an issue that was newly introduced in 7.2.10 and the LSI patches improve the reentrancy fix. The others also sounded relevant and nice to have. Signed-off-by: Fiona Ebner <f.ebner@proxmox.com>
92 lines
3.8 KiB
Diff
92 lines
3.8 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Peter Maydell <peter.maydell@linaro.org>
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Date: Wed, 10 Apr 2024 08:43:25 +0300
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Subject: [PATCH] tests/tcg/aarch64/sysregs.c: Use S syntax for id_aa64zfr0_el1
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and id_aa64smfr0_el1
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Some assemblers will complain about attempts to access
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id_aa64zfr0_el1 and id_aa64smfr0_el1 by name if the test
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binary isn't built for the right processor type:
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/tmp/ccASXpLo.s:782: Error: selected processor does not support system register name 'id_aa64zfr0_el1'
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/tmp/ccASXpLo.s:829: Error: selected processor does not support system register name 'id_aa64smfr0_el1'
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However, these registers are in the ID space and are guaranteed to
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read-as-zero on older CPUs, so the access is both safe and sensible.
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Switch to using the S syntax, as we already do for ID_AA64ISAR2_EL1
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and ID_AA64MMFR2_EL1. This allows us to drop the HAS_ARMV9_SME check
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and the makefile machinery to adjust the CFLAGS for this test, so we
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don't rely on having a sufficiently new compiler to be able to check
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these registers.
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This means we're actually testing the SME ID register: no released
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GCC yet recognizes -march=armv9-a+sme, so that was always skipped.
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It also avoids a future problem if we try to switch the "do we have
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SME support in the toolchain" check from "in the compiler" to "in the
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assembler" (at which point we would otherwise run into the above
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errors).
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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(cherry picked from commit 3dc2afeab2964b54848715b913b6c605f36be3e1)
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Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
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(Mjt: pick this for v8.0.0-2361-g1f51573f79
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"target/arm: Fix SME full tile indexing")
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---
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tests/tcg/aarch64/Makefile.target | 7 +------
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tests/tcg/aarch64/sysregs.c | 11 +++++++----
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2 files changed, 8 insertions(+), 10 deletions(-)
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diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
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index fc6d5d824d..118d069073 100644
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--- a/tests/tcg/aarch64/Makefile.target
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+++ b/tests/tcg/aarch64/Makefile.target
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@@ -51,15 +51,10 @@ AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-5 mte-6 mte-7
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mte-%: CFLAGS += -march=armv8.5-a+memtag
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endif
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-ifneq ($(CROSS_CC_HAS_SVE),)
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# System Registers Tests
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AARCH64_TESTS += sysregs
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-ifneq ($(CROSS_CC_HAS_ARMV9_SME),)
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-sysregs: CFLAGS+=-march=armv9-a+sme -DHAS_ARMV9_SME
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-else
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-sysregs: CFLAGS+=-march=armv8.1-a+sve
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-endif
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+ifneq ($(CROSS_CC_HAS_SVE),)
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# SVE ioctl test
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AARCH64_TESTS += sve-ioctls
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sve-ioctls: CFLAGS+=-march=armv8.1-a+sve
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diff --git a/tests/tcg/aarch64/sysregs.c b/tests/tcg/aarch64/sysregs.c
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index 46b931f781..d8eb06abcf 100644
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--- a/tests/tcg/aarch64/sysregs.c
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+++ b/tests/tcg/aarch64/sysregs.c
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@@ -25,9 +25,14 @@
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/*
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* Older assemblers don't recognize newer system register names,
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* but we can still access them by the Sn_n_Cn_Cn_n syntax.
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+ * This also means we don't need to specifically request that the
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+ * assembler enables whatever architectural features the ID registers
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+ * syntax might be gated behind.
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*/
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#define SYS_ID_AA64ISAR2_EL1 S3_0_C0_C6_2
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#define SYS_ID_AA64MMFR2_EL1 S3_0_C0_C7_2
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+#define SYS_ID_AA64ZFR0_EL1 S3_0_C0_C4_4
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+#define SYS_ID_AA64SMFR0_EL1 S3_0_C0_C4_5
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int failed_bit_count;
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@@ -132,10 +137,8 @@ int main(void)
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/* all hidden, DebugVer fixed to 0x6 (ARMv8 debug architecture) */
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get_cpu_reg_check_mask(id_aa64dfr0_el1, _m(0000,0000,0000,0006));
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get_cpu_reg_check_zero(id_aa64dfr1_el1);
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- get_cpu_reg_check_mask(id_aa64zfr0_el1, _m(0ff0,ff0f,00ff,00ff));
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-#ifdef HAS_ARMV9_SME
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- get_cpu_reg_check_mask(id_aa64smfr0_el1, _m(80f1,00fd,0000,0000));
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-#endif
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+ get_cpu_reg_check_mask(SYS_ID_AA64ZFR0_EL1, _m(0ff0,ff0f,00ff,00ff));
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+ get_cpu_reg_check_mask(SYS_ID_AA64SMFR0_EL1, _m(80f1,00fd,0000,0000));
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get_cpu_reg_check_zero(id_aa64afr0_el1);
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get_cpu_reg_check_zero(id_aa64afr1_el1);
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