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d2ced986db
cherry-picks mds mitigation related commits from upstream qemu, some commits are taken to ensure easy backport. fixes included for: * CVE-2018-12126 * CVE-2018-12127 * CVE-2018-12130 * CVE-2019-11091 adds the md-clear cpuflag. Not included by default in any Intel CPU model. Must be explicitly turned on for all Intel CPU models. Requires the host CPU microcode to support this feature before it can be used for guest CPUs. Signed-off-by: Oguz Bektas <o.bektas@proxmox.com>
39 lines
1.5 KiB
Diff
39 lines
1.5 KiB
Diff
From 745b4afa5ece8aa17306ca07e48ae9cb64161e6d Mon Sep 17 00:00:00 2001
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From: Robert Hoo <robert.hu@linux.intel.com>
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Date: Thu, 5 Jul 2018 17:09:54 +0800
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Subject: [PATCH] i386: Add new MSR indices for IA32_PRED_CMD and
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IA32_ARCH_CAPABILITIES
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IA32_PRED_CMD MSR gives software a way to issue commands that affect the state
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of indirect branch predictors. Enumerated by CPUID.(EAX=7H,ECX=0):EDX[26].
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IA32_ARCH_CAPABILITIES MSR enumerates architectural features of RDCL_NO and
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IBRS_ALL. Enumerated by CPUID.(EAX=07H, ECX=0):EDX[29].
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https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf
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Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
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Message-Id: <1530781798-183214-2-git-send-email-robert.hu@linux.intel.com>
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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(cherry picked from commit 8c80c99fcceabd0708a5a83f08577e778c9419f5)
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Signed-off-by: Oguz Bektas <o.bektas@proxmox.com>
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---
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target/i386/cpu.h | 2 ++
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1 file changed, 2 insertions(+)
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 58ae637edc..fb2f5f6ebc 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -354,6 +354,8 @@ typedef enum X86Seg {
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#define MSR_TSC_ADJUST 0x0000003b
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#define MSR_IA32_SPEC_CTRL 0x48
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#define MSR_VIRT_SSBD 0xc001011f
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+#define MSR_IA32_PRED_CMD 0x49
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+#define MSR_IA32_ARCH_CAPABILITIES 0x10a
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#define MSR_IA32_TSCDEADLINE 0x6e0
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#define FEATURE_CONTROL_LOCKED (1<<0)
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--
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2.11.0
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