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72d241207c
Cherry-pick upstream commit f24f669d03f884a6ef95cca84317d0f329e93961 to avoid unnecessary performance penalty for setups with a new enough CPU microcode update applied. Signed-off-by: Thomas Lamprecht <t.lamprecht@proxmox.com>
79 lines
2.9 KiB
Diff
79 lines
2.9 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Xi Ruoyao <xry111@xry111.site>
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Date: Wed, 22 May 2024 10:06:24 +0800
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Subject: [PATCH] x86/mm: Don't disable PCID when INVLPG has been fixed by
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microcode
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Per the "Processor Specification Update" documentations referred by
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the intel-microcode-20240312 release note, this microcode release has
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fixed the issue for all affected models.
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So don't disable PCID if the microcode is new enough. The precise
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minimum microcode revision fixing the issue was provided by Pawan
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Intel.
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[ dhansen: comment and changelog tweaks ]
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Signed-off-by: Xi Ruoyao <xry111@xry111.site>
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Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
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Acked-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
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Link: https://lore.kernel.org/all/168436059559.404.13934972543631851306.tip-bot2@tip-bot2/
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Link: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20240312
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Link: https://cdrdv2.intel.com/v1/dl/getContent/740518 # RPL042, rev. 13
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Link: https://cdrdv2.intel.com/v1/dl/getContent/682436 # ADL063, rev. 24
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Link: https://lore.kernel.org/all/20240325231300.qrltbzf6twm43ftb@desk/
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Link: https://lore.kernel.org/all/20240522020625.69418-1-xry111%40xry111.site
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(cherry-picked from f24f669d03f884a6ef95cca84317d0f329e93961)
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Signed-off-by: Thomas Lamprecht <t.lamprecht@proxmox.com>
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---
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arch/x86/mm/init.c | 23 ++++++++++++++---------
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1 file changed, 14 insertions(+), 9 deletions(-)
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diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
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index eb503f53c3195ca4f299593c0112dab0fb09e7dd..101725c149c4294f22e337845e01c82dfe71cde5 100644
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--- a/arch/x86/mm/init.c
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+++ b/arch/x86/mm/init.c
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@@ -263,28 +263,33 @@ static void __init probe_page_size_mask(void)
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}
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/*
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- * INVLPG may not properly flush Global entries
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- * on these CPUs when PCIDs are enabled.
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+ * INVLPG may not properly flush Global entries on
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+ * these CPUs. New microcode fixes the issue.
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*/
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static const struct x86_cpu_id invlpg_miss_ids[] = {
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- X86_MATCH_VFM(INTEL_ALDERLAKE, 0),
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- X86_MATCH_VFM(INTEL_ALDERLAKE_L, 0),
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- X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, 0),
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- X86_MATCH_VFM(INTEL_RAPTORLAKE, 0),
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- X86_MATCH_VFM(INTEL_RAPTORLAKE_P, 0),
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- X86_MATCH_VFM(INTEL_RAPTORLAKE_S, 0),
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+ X86_MATCH_VFM(INTEL_ALDERLAKE, 0x2e),
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+ X86_MATCH_VFM(INTEL_ALDERLAKE_L, 0x42c),
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+ X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, 0x11),
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+ X86_MATCH_VFM(INTEL_RAPTORLAKE, 0x118),
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+ X86_MATCH_VFM(INTEL_RAPTORLAKE_P, 0x4117),
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+ X86_MATCH_VFM(INTEL_RAPTORLAKE_S, 0x2e),
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{}
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};
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static void setup_pcid(void)
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{
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+ const struct x86_cpu_id *invlpg_miss_match;
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+
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if (!IS_ENABLED(CONFIG_X86_64))
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return;
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if (!boot_cpu_has(X86_FEATURE_PCID))
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return;
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- if (x86_match_cpu(invlpg_miss_ids)) {
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+ invlpg_miss_match = x86_match_cpu(invlpg_miss_ids);
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+
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+ if (invlpg_miss_match &&
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+ boot_cpu_data.microcode < invlpg_miss_match->driver_data) {
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pr_info("Incomplete global flushes, disabling PCID");
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setup_clear_cpu_cap(X86_FEATURE_PCID);
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return;
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