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4254e40729
This adds basic support for RISC-V, specifically RV64G. Reviewed-by: Brian Behlendorf <behlendorf1@llnl.gov> Signed-off-by: Romain Dolbeau <romain.dolbeau@european-processor-initiative.eu> Closes #9540
92 lines
2.9 KiB
ArmAsm
92 lines
2.9 KiB
ArmAsm
/*-
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* Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Portions of this software were developed by SRI International and the
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* University of Cambridge Computer Laboratory under DARPA/AFRL contract
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* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Portions of this software were developed by the University of Cambridge
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* Computer Laboratory as part of the CTSRD Project, with support from the
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* UK Higher Education Innovation Fund (HEIF).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#define ENTRY(sym) \
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.text; .globl sym; .type sym,@function; sym:
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#define END(sym) .size sym, . - sym
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ENTRY(setjmp)
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/* Store the stack pointer */
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sd sp, (0 * 8)(a0)
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addi a0, a0, (1 * 8)
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/* Store the general purpose registers and ra */
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sd s0, (0 * 8)(a0)
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sd s1, (1 * 8)(a0)
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sd s2, (2 * 8)(a0)
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sd s3, (3 * 8)(a0)
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sd s4, (4 * 8)(a0)
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sd s5, (5 * 8)(a0)
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sd s6, (6 * 8)(a0)
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sd s7, (7 * 8)(a0)
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sd s8, (8 * 8)(a0)
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sd s9, (9 * 8)(a0)
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sd s10, (10 * 8)(a0)
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sd s11, (11 * 8)(a0)
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sd ra, (12 * 8)(a0)
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addi a0, a0, (13 * 8)
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/* Return value */
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li a0, 0
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ret
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END(setjmp)
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ENTRY(longjmp)
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/* Restore the stack pointer */
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ld t0, 0(a0)
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mv sp, t0
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addi a0, a0, (1 * 8)
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/* Restore the general purpose registers and ra */
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ld s0, (0 * 8)(a0)
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ld s1, (1 * 8)(a0)
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ld s2, (2 * 8)(a0)
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ld s3, (3 * 8)(a0)
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ld s4, (4 * 8)(a0)
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ld s5, (5 * 8)(a0)
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ld s6, (6 * 8)(a0)
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ld s7, (7 * 8)(a0)
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ld s8, (8 * 8)(a0)
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ld s9, (9 * 8)(a0)
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ld s10, (10 * 8)(a0)
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ld s11, (11 * 8)(a0)
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ld ra, (12 * 8)(a0)
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addi a0, a0, (13 * 8)
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/* Load the return value */
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mv a0, a1
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ret
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END(longjmp)
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