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d465fc5844
Reviewed-by: Brian Behlendorf <behlendorf1@llnl.gov> Signed-off-by: Ahelenia Ziemiańska <nabijaczleweli@nabijaczleweli.xyz> Closes #12996
235 lines
7.0 KiB
C
235 lines
7.0 KiB
C
/*
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* Implement fast Fletcher4 with SSE2,SSSE3 instructions. (x86)
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*
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* Use the 128-bit SSE2/SSSE3 SIMD instructions and registers to compute
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* Fletcher4 in two incremental 64-bit parallel accumulator streams,
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* and then combine the streams to form the final four checksum words.
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* This implementation is a derivative of the AVX SIMD implementation by
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* James Guilford and Jinshan Xiong from Intel (see zfs_fletcher_intel.c).
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*
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* Copyright (C) 2016 Tyler J. Stachecki.
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*
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* Authors:
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* Tyler J. Stachecki <stachecki.tyler@gmail.com>
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#if defined(HAVE_SSE2)
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#include <sys/simd.h>
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#include <sys/spa_checksum.h>
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#include <sys/string.h>
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#include <sys/byteorder.h>
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#include <zfs_fletcher.h>
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ZFS_NO_SANITIZE_UNDEFINED
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static void
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fletcher_4_sse2_init(fletcher_4_ctx_t *ctx)
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{
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memset(ctx->sse, 0, 4 * sizeof (zfs_fletcher_sse_t));
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}
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ZFS_NO_SANITIZE_UNDEFINED
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static void
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fletcher_4_sse2_fini(fletcher_4_ctx_t *ctx, zio_cksum_t *zcp)
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{
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uint64_t A, B, C, D;
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/*
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* The mixing matrix for checksum calculation is:
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* a = a0 + a1
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* b = 2b0 + 2b1 - a1
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* c = 4c0 - b0 + 4c1 -3b1
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* d = 8d0 - 4c0 + 8d1 - 8c1 + b1;
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*
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* c and d are multiplied by 4 and 8, respectively,
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* before spilling the vectors out to memory.
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*/
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A = ctx->sse[0].v[0] + ctx->sse[0].v[1];
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B = 2 * ctx->sse[1].v[0] + 2 * ctx->sse[1].v[1] - ctx->sse[0].v[1];
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C = 4 * ctx->sse[2].v[0] - ctx->sse[1].v[0] + 4 * ctx->sse[2].v[1] -
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3 * ctx->sse[1].v[1];
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D = 8 * ctx->sse[3].v[0] - 4 * ctx->sse[2].v[0] + 8 * ctx->sse[3].v[1] -
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8 * ctx->sse[2].v[1] + ctx->sse[1].v[1];
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ZIO_SET_CHECKSUM(zcp, A, B, C, D);
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}
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#define FLETCHER_4_SSE_RESTORE_CTX(ctx) \
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{ \
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asm volatile("movdqu %0, %%xmm0" :: "m" ((ctx)->sse[0])); \
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asm volatile("movdqu %0, %%xmm1" :: "m" ((ctx)->sse[1])); \
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asm volatile("movdqu %0, %%xmm2" :: "m" ((ctx)->sse[2])); \
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asm volatile("movdqu %0, %%xmm3" :: "m" ((ctx)->sse[3])); \
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}
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#define FLETCHER_4_SSE_SAVE_CTX(ctx) \
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{ \
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asm volatile("movdqu %%xmm0, %0" : "=m" ((ctx)->sse[0])); \
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asm volatile("movdqu %%xmm1, %0" : "=m" ((ctx)->sse[1])); \
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asm volatile("movdqu %%xmm2, %0" : "=m" ((ctx)->sse[2])); \
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asm volatile("movdqu %%xmm3, %0" : "=m" ((ctx)->sse[3])); \
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}
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static void
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fletcher_4_sse2_native(fletcher_4_ctx_t *ctx, const void *buf, uint64_t size)
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{
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const uint64_t *ip = buf;
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const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size);
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kfpu_begin();
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FLETCHER_4_SSE_RESTORE_CTX(ctx);
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asm volatile("pxor %xmm4, %xmm4");
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for (; ip < ipend; ip += 2) {
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asm volatile("movdqu %0, %%xmm5" :: "m"(*ip));
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asm volatile("movdqa %xmm5, %xmm6");
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asm volatile("punpckldq %xmm4, %xmm5");
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asm volatile("punpckhdq %xmm4, %xmm6");
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asm volatile("paddq %xmm5, %xmm0");
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asm volatile("paddq %xmm0, %xmm1");
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asm volatile("paddq %xmm1, %xmm2");
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asm volatile("paddq %xmm2, %xmm3");
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asm volatile("paddq %xmm6, %xmm0");
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asm volatile("paddq %xmm0, %xmm1");
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asm volatile("paddq %xmm1, %xmm2");
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asm volatile("paddq %xmm2, %xmm3");
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}
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FLETCHER_4_SSE_SAVE_CTX(ctx);
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kfpu_end();
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}
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static void
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fletcher_4_sse2_byteswap(fletcher_4_ctx_t *ctx, const void *buf, uint64_t size)
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{
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const uint32_t *ip = buf;
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const uint32_t *ipend = (uint32_t *)((uint8_t *)ip + size);
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kfpu_begin();
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FLETCHER_4_SSE_RESTORE_CTX(ctx);
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for (; ip < ipend; ip += 2) {
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uint32_t scratch1 = BSWAP_32(ip[0]);
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uint32_t scratch2 = BSWAP_32(ip[1]);
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asm volatile("movd %0, %%xmm5" :: "r"(scratch1));
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asm volatile("movd %0, %%xmm6" :: "r"(scratch2));
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asm volatile("punpcklqdq %xmm6, %xmm5");
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asm volatile("paddq %xmm5, %xmm0");
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asm volatile("paddq %xmm0, %xmm1");
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asm volatile("paddq %xmm1, %xmm2");
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asm volatile("paddq %xmm2, %xmm3");
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}
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FLETCHER_4_SSE_SAVE_CTX(ctx);
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kfpu_end();
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}
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static boolean_t fletcher_4_sse2_valid(void)
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{
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return (kfpu_allowed() && zfs_sse2_available());
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}
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const fletcher_4_ops_t fletcher_4_sse2_ops = {
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.init_native = fletcher_4_sse2_init,
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.fini_native = fletcher_4_sse2_fini,
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.compute_native = fletcher_4_sse2_native,
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.init_byteswap = fletcher_4_sse2_init,
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.fini_byteswap = fletcher_4_sse2_fini,
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.compute_byteswap = fletcher_4_sse2_byteswap,
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.valid = fletcher_4_sse2_valid,
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.name = "sse2"
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};
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#endif /* defined(HAVE_SSE2) */
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#if defined(HAVE_SSE2) && defined(HAVE_SSSE3)
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static void
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fletcher_4_ssse3_byteswap(fletcher_4_ctx_t *ctx, const void *buf, uint64_t size)
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{
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static const zfs_fletcher_sse_t mask = {
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.v = { 0x0405060700010203, 0x0C0D0E0F08090A0B }
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};
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const uint64_t *ip = buf;
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const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size);
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kfpu_begin();
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FLETCHER_4_SSE_RESTORE_CTX(ctx);
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asm volatile("movdqu %0, %%xmm7"::"m" (mask));
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asm volatile("pxor %xmm4, %xmm4");
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for (; ip < ipend; ip += 2) {
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asm volatile("movdqu %0, %%xmm5"::"m" (*ip));
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asm volatile("pshufb %xmm7, %xmm5");
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asm volatile("movdqa %xmm5, %xmm6");
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asm volatile("punpckldq %xmm4, %xmm5");
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asm volatile("punpckhdq %xmm4, %xmm6");
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asm volatile("paddq %xmm5, %xmm0");
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asm volatile("paddq %xmm0, %xmm1");
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asm volatile("paddq %xmm1, %xmm2");
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asm volatile("paddq %xmm2, %xmm3");
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asm volatile("paddq %xmm6, %xmm0");
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asm volatile("paddq %xmm0, %xmm1");
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asm volatile("paddq %xmm1, %xmm2");
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asm volatile("paddq %xmm2, %xmm3");
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}
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FLETCHER_4_SSE_SAVE_CTX(ctx);
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kfpu_end();
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}
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static boolean_t fletcher_4_ssse3_valid(void)
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{
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return (kfpu_allowed() && zfs_sse2_available() &&
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zfs_ssse3_available());
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}
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const fletcher_4_ops_t fletcher_4_ssse3_ops = {
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.init_native = fletcher_4_sse2_init,
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.fini_native = fletcher_4_sse2_fini,
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.compute_native = fletcher_4_sse2_native,
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.init_byteswap = fletcher_4_sse2_init,
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.fini_byteswap = fletcher_4_sse2_fini,
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.compute_byteswap = fletcher_4_ssse3_byteswap,
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.valid = fletcher_4_ssse3_valid,
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.name = "ssse3"
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};
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#endif /* defined(HAVE_SSE2) && defined(HAVE_SSSE3) */
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