Dillon Varone fdf7d4f547 drm/amd/display: Report Proper Quantization Range in AVI Infoframe ... [Why?] When a monitor does not set both QS and QY bits, DC does not set Q0, Q1, QY0 and QY1 bits in AVI infoframe. Setting RGB bits should be separate from setting YCC bits. [How?] Separate logic for setting RGB and YCC quantization range bits in the AVI infoframe. Signed-off-by: Dillon Varone <dillon.varone@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-04-20 21:42:38 -04:00
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acp	drm: amd/acp: fix broken menu structure	2020-03-13 11:52:35 -04:00
amdgpu	drm/amdgpu: fix GCR_GENERAL_CNTL offset for dimgrey_cavefish	2021-04-20 21:36:28 -04:00
amdkfd	drm/amdkfd: add edc error interrupt handle for poison propogate mode	2021-04-20 21:35:13 -04:00
display	drm/amd/display: Report Proper Quantization Range in AVI Infoframe	2021-04-20 21:42:38 -04:00
include	drm/amdgpu: only harvest gcea/mmea error status in arcturus	2021-04-20 21:35:45 -04:00
pm	drm/amd/pm: fix error code in smu_set_power_limit()	2021-04-15 16:32:45 -04:00