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77a512e35d
There are a few MSRs and control register bits that the kernel normally needs to modify during boot. But, TDX disallows modification of these registers to help provide consistent security guarantees. Fortunately, TDX ensures that these are all in the correct state before the kernel loads, which means the kernel does not need to modify them. The conditions to avoid are: * Any writes to the EFER MSR * Clearing CR4.MCE This theoretically makes the guest boot more fragile. If, for instance, EFER was set up incorrectly and a WRMSR was performed, it will trigger early exception panic or a triple fault, if it's before early exceptions are set up. However, this is likely to trip up the guest BIOS long before control reaches the kernel. In any case, these kinds of problems are unlikely to occur in production environments, and developers have good debug tools to fix them quickly. Change the common boot code to work on TDX and non-TDX systems. This should have no functional effect on non-TDX systems. Signed-off-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Reviewed-by: Andi Kleen <ak@linux.intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/20220405232939.73860-24-kirill.shutemov@linux.intel.com
247 lines
6.1 KiB
ArmAsm
247 lines
6.1 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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*
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* Trampoline.S Derived from Setup.S by Linus Torvalds
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*
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* 4 Jan 1997 Michael Chastain: changed to gnu as.
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* 15 Sept 2005 Eric Biederman: 64bit PIC support
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*
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* Entry: CS:IP point to the start of our code, we are
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* in real mode with no stack, but the rest of the
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* trampoline page to make our stack and everything else
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* is a mystery.
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*
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* On entry to trampoline_start, the processor is in real mode
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* with 16-bit addressing and 16-bit data. CS has some value
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* and IP is zero. Thus, data addresses need to be absolute
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* (no relocation) and are taken with regard to r_base.
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*
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* With the addition of trampoline_level4_pgt this code can
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* now enter a 64bit kernel that lives at arbitrary 64bit
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* physical addresses.
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*
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* If you work on this file, check the object module with objdump
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* --full-contents --reloc to make sure there are no relocation
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* entries.
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*/
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#include <linux/linkage.h>
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#include <asm/pgtable_types.h>
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#include <asm/page_types.h>
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#include <asm/msr.h>
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#include <asm/segment.h>
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#include <asm/processor-flags.h>
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#include <asm/realmode.h>
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#include "realmode.h"
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.text
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.code16
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.balign PAGE_SIZE
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SYM_CODE_START(trampoline_start)
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cli # We should be safe anyway
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wbinvd
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LJMPW_RM(1f)
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1:
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mov %cs, %ax # Code and data in the same place
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mov %ax, %ds
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mov %ax, %es
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mov %ax, %ss
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# Setup stack
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movl $rm_stack_end, %esp
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call verify_cpu # Verify the cpu supports long mode
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testl %eax, %eax # Check for return code
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jnz no_longmode
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.Lswitch_to_protected:
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/*
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* GDT tables in non default location kernel can be beyond 16MB and
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* lgdt will not be able to load the address as in real mode default
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* operand size is 16bit. Use lgdtl instead to force operand size
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* to 32 bit.
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*/
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lidtl tr_idt # load idt with 0, 0
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lgdtl tr_gdt # load gdt with whatever is appropriate
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movw $__KERNEL_DS, %dx # Data segment descriptor
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# Enable protected mode
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movl $(CR0_STATE & ~X86_CR0_PG), %eax
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movl %eax, %cr0 # into protected mode
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# flush prefetch and jump to startup_32
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ljmpl $__KERNEL32_CS, $pa_startup_32
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no_longmode:
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hlt
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jmp no_longmode
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SYM_CODE_END(trampoline_start)
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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/* SEV-ES supports non-zero IP for entry points - no alignment needed */
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SYM_CODE_START(sev_es_trampoline_start)
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cli # We should be safe anyway
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LJMPW_RM(1f)
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1:
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mov %cs, %ax # Code and data in the same place
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mov %ax, %ds
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mov %ax, %es
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mov %ax, %ss
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# Setup stack
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movl $rm_stack_end, %esp
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jmp .Lswitch_to_protected
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SYM_CODE_END(sev_es_trampoline_start)
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#endif /* CONFIG_AMD_MEM_ENCRYPT */
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#include "../kernel/verify_cpu.S"
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.section ".text32","ax"
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.code32
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.balign 4
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SYM_CODE_START(startup_32)
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movl %edx, %ss
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addl $pa_real_mode_base, %esp
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movl %edx, %ds
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movl %edx, %es
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movl %edx, %fs
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movl %edx, %gs
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/*
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* Check for memory encryption support. This is a safety net in
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* case BIOS hasn't done the necessary step of setting the bit in
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* the MSR for this AP. If SME is active and we've gotten this far
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* then it is safe for us to set the MSR bit and continue. If we
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* don't we'll eventually crash trying to execute encrypted
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* instructions.
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*/
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btl $TH_FLAGS_SME_ACTIVE_BIT, pa_tr_flags
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jnc .Ldone
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movl $MSR_AMD64_SYSCFG, %ecx
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rdmsr
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bts $MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT, %eax
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jc .Ldone
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/*
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* Memory encryption is enabled but the SME enable bit for this
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* CPU has has not been set. It is safe to set it, so do so.
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*/
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wrmsr
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.Ldone:
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movl pa_tr_cr4, %eax
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movl %eax, %cr4 # Enable PAE mode
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# Setup trampoline 4 level pagetables
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movl $pa_trampoline_pgd, %eax
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movl %eax, %cr3
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# Set up EFER
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movl $MSR_EFER, %ecx
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rdmsr
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/*
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* Skip writing to EFER if the register already has desired
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* value (to avoid #VE for the TDX guest).
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*/
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cmp pa_tr_efer, %eax
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jne .Lwrite_efer
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cmp pa_tr_efer + 4, %edx
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je .Ldone_efer
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.Lwrite_efer:
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movl pa_tr_efer, %eax
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movl pa_tr_efer + 4, %edx
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wrmsr
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.Ldone_efer:
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# Enable paging and in turn activate Long Mode.
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movl $CR0_STATE, %eax
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movl %eax, %cr0
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/*
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* At this point we're in long mode but in 32bit compatibility mode
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* with EFER.LME = 1, CS.L = 0, CS.D = 1 (and in turn
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* EFER.LMA = 1). Now we want to jump in 64bit mode, to do that we use
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* the new gdt/idt that has __KERNEL_CS with CS.L = 1.
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*/
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ljmpl $__KERNEL_CS, $pa_startup_64
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SYM_CODE_END(startup_32)
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SYM_CODE_START(pa_trampoline_compat)
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/*
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* In compatibility mode. Prep ESP and DX for startup_32, then disable
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* paging and complete the switch to legacy 32-bit mode.
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*/
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movl $rm_stack_end, %esp
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movw $__KERNEL_DS, %dx
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movl $(CR0_STATE & ~X86_CR0_PG), %eax
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movl %eax, %cr0
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ljmpl $__KERNEL32_CS, $pa_startup_32
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SYM_CODE_END(pa_trampoline_compat)
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.section ".text64","ax"
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.code64
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.balign 4
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SYM_CODE_START(startup_64)
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# Now jump into the kernel using virtual addresses
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jmpq *tr_start(%rip)
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SYM_CODE_END(startup_64)
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SYM_CODE_START(trampoline_start64)
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/*
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* APs start here on a direct transfer from 64-bit BIOS with identity
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* mapped page tables. Load the kernel's GDT in order to gear down to
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* 32-bit mode (to handle 4-level vs. 5-level paging), and to (re)load
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* segment registers. Load the zero IDT so any fault triggers a
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* shutdown instead of jumping back into BIOS.
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*/
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lidt tr_idt(%rip)
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lgdt tr_gdt64(%rip)
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ljmpl *tr_compat(%rip)
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SYM_CODE_END(trampoline_start64)
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.section ".rodata","a"
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# Duplicate the global descriptor table
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# so the kernel can live anywhere
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.balign 16
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SYM_DATA_START(tr_gdt)
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.short tr_gdt_end - tr_gdt - 1 # gdt limit
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.long pa_tr_gdt
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.short 0
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.quad 0x00cf9b000000ffff # __KERNEL32_CS
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.quad 0x00af9b000000ffff # __KERNEL_CS
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.quad 0x00cf93000000ffff # __KERNEL_DS
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SYM_DATA_END_LABEL(tr_gdt, SYM_L_LOCAL, tr_gdt_end)
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SYM_DATA_START(tr_gdt64)
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.short tr_gdt_end - tr_gdt - 1 # gdt limit
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.long pa_tr_gdt
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.long 0
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SYM_DATA_END(tr_gdt64)
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SYM_DATA_START(tr_compat)
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.long pa_trampoline_compat
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.short __KERNEL32_CS
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SYM_DATA_END(tr_compat)
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.bss
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.balign PAGE_SIZE
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SYM_DATA(trampoline_pgd, .space PAGE_SIZE)
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.balign 8
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SYM_DATA_START(trampoline_header)
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SYM_DATA_LOCAL(tr_start, .space 8)
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SYM_DATA(tr_efer, .space 8)
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SYM_DATA(tr_cr4, .space 4)
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SYM_DATA(tr_flags, .space 4)
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SYM_DATA_END(trampoline_header)
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#include "trampoline_common.S"
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