Wenjing Liu f77d1a4990 drm/amd/display: fix a regression in blank pixel data caused by coding mistake ... [why] There was unfortunately a coding mistake. It gets caught with an ultrawide monitor that requires ODM 4:1 combine. We are blanking or unblanking pixel data we are supposed to enumerate through all ODM pipes and program DPG for each of those pipes. However the coding mistake causes us to program only the first and last ODM pipes. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by: Martin Leung <martin.leung@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2023-08-07 17:14:07 -04:00
..
amdgpu_dm	drm/amd/display: ensure async flips are only accepted for fast updates	2023-08-07 17:14:07 -04:00
dc	drm/amd/display: fix a regression in blank pixel data caused by coding mistake	2023-08-07 17:14:07 -04:00
dmub	drm/amd/display: Add structs for Freesync Panel Replay	2023-08-07 17:12:49 -04:00
include	drm/amd/display: Read replay data from sink	2023-08-07 17:14:07 -04:00
modules	drm/amd/display: Add Freesync Panel DM code	2023-08-07 17:14:07 -04:00
Kconfig	drm/amd/display: Allow building DC with clang on RISC-V	2023-07-21 16:52:25 -04:00
Makefile	drm/amd/display: Drop CONFIG_DRM_AMD_DC_HDCP	2023-03-07 14:22:39 -05:00
TODO