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Currently, the size of the ASID field in the MM context ID dynamically depends on the number of hardware-supported ASID bits. This requires reading a global variable to extract either field from the context ID. Instead, allocate the maximum possible number of bits to the ASID field, so the layout of the context ID is known at compile-time. Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20240327045035.368512-11-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
37 lines
826 B
C
37 lines
826 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_MMU_H
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#define _ASM_RISCV_MMU_H
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#ifndef __ASSEMBLY__
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typedef struct {
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#ifndef CONFIG_MMU
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unsigned long end_brk;
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#else
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atomic_long_t id;
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#endif
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void *vdso;
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#ifdef CONFIG_SMP
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/* A local icache flush is needed before user execution can resume. */
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cpumask_t icache_stale_mask;
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#endif
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#ifdef CONFIG_BINFMT_ELF_FDPIC
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unsigned long exec_fdpic_loadmap;
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unsigned long interp_fdpic_loadmap;
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#endif
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} mm_context_t;
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#define cntx2asid(cntx) ((cntx) & SATP_ASID_MASK)
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#define cntx2version(cntx) ((cntx) & ~SATP_ASID_MASK)
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void __init create_pgd_mapping(pgd_t *pgdp, uintptr_t va, phys_addr_t pa,
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phys_addr_t sz, pgprot_t prot);
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_RISCV_MMU_H */
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