Tim Huang f1373a97a4 drm/amd/pm: reverse mclk and fclk clocks levels for yellow carp ... This patch reverses the DPM clocks levels output of pp_dpm_mclk and pp_dpm_fclk. On dGPUs and older APUs we expose the levels from lowest clocks to highest clocks. But for some APUs, the clocks levels that from the DFPstateTable are given the reversed orders by PMFW. Like the memory DPM clocks that are exposed by pp_dpm_mclk. It's not intuitive that they are reversed on these APUs. All tools and software that talks to the driver then has to know different ways to interpret the data depending on the asic. So we need to reverse them to expose the clocks levels from the driver consistently. Signed-off-by: Tim Huang <Tim.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org		2023-05-31 16:48:05 -04:00
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inc	drm/amdgpu: added a sysfs interface for thermal throttling	2023-02-23 17:36:00 -05:00
legacy-dpm	drm/amd: Use amdgpu_ucode_release helper for si	2023-01-10 14:32:58 -05:00
powerplay	drm/amd/pm: avoid unaligned access warnings	2023-02-15 22:25:01 -05:00
swsmu	drm/amd/pm: reverse mclk and fclk clocks levels for yellow carp	2023-05-31 16:48:05 -04:00
amdgpu_dpm_internal.c	drm/amd/pm: add missing prototypes to amdgpu_dpm_internal	2022-02-07 18:03:50 -05:00
amdgpu_dpm.c	drm/amd/pm: avoid potential UBSAN issue on legacy asics	2023-05-11 08:41:36 -04:00
amdgpu_pm.c	drm/amd/pm: Fix output of pp_od_clk_voltage	2023-05-24 15:18:10 -04:00
Makefile	drm/amd/pm: relocate the power related headers	2022-01-14 17:51:14 -05:00