George Shen f031ba1208 drm/amd/display: Update test link rate DPCD bit field to match spec ... [Why] An SCR was made to the DP2.0 spec that updated the bit field definition for UHBR13.5 in the test link rate DPCD register. [How] Add new translation to match the SCR update. Keep old translation for backwards compatibility. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2023-11-07 11:17:11 -05:00
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drm	drm/amd/display: Update test link rate DPCD bit field to match spec	2023-11-07 11:17:11 -05:00
host1x	gpu: host1x: Correct allocated size for contexts	2023-10-11 22:52:44 +02:00
ipu-v3	drm for 6.6-rc1	2023-08-30 13:34:34 -07:00
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