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The attached patches provides part 7 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org> |
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| .. | ||
| config-linux_be | ||
| cacheasm.h | ||
| cacheattrasm.h | ||
| coreasm.h | ||
| corebits.h | ||
| hal.h | ||
| simcall.h | ||
| xt2000-uart.h | ||
| xt2000.h | ||
| xtboard.h | ||