Srinivasan Shanmugam edf176f48d drm/i915/dg2: Move misplaced 'ctx' & 'gt' wa's to engine wa list ... Registers that belong to the shared render/compute reset domain need to be placed on an engine workaround list to ensure that they are properly re-applied whenever any RCS or CCS engine is reset, even if the registers do not belong to a specific engine's MMIO range. We have a number of workarounds today that are incorrectly implemented on the 'gt' workaround list and need to be moved accordingly. We also have one workaround (Wa_22012532006) that is incorrectly implemented on the context workaround list, even though the register it is adjusting is not part of the RCS engine's context image; it must also be moved. We'll have some workaround refactoring coming in the near future that deals with registers in the reset domain in a more clear way. But in the meantime, we should just move these workarounds to rcs_engine_wa_init() to place them on the RCS engine's workaround list. All production DG2 platforms will have an RCS engine (it's never fused off) so these registers will be properly restored after a domain reset triggered via an RCS engine _or_ a CCS engine. Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.s@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220215235531.2236399-1-matthew.d.roper@intel.com		2022-02-17 13:39:10 -08:00
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drm	drm/i915/dg2: Move misplaced 'ctx' & 'gt' wa's to engine wa list	2022-02-17 13:39:10 -08:00
host1x	gpu: host1x: Add back arm_iommu_detach_device()	2021-12-16 14:28:51 +01:00
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