Conor Dooley 0dec364ffe riscv: dts: microchip: use an mpfs specific l2 compatible ... PolarFire SoC does not have the same l2 cache controller as the fu540, featuring an extra interrupt. Appease the devicetree checker overlords by adding a PolarFire SoC specific compatible to fix the below sort of warnings: mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], [2]] is too long Fixes: 0fa6107eca ("RISC-V: Initial DTS for Microchip ICICLE board") Fixes: 34fc9cc3ae ("riscv: dts: microchip: correct L2 cache interrupts") Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>		2022-08-31 16:57:51 +01:00
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canaan	RISC-V: Canaan devicetree fixes	2022-08-10 14:43:14 -07:00
microchip	riscv: dts: microchip: use an mpfs specific l2 compatible	2022-08-31 16:57:51 +01:00
sifive	riscv: dts: sifive unmatched: Add PWM controlled LEDs	2022-08-11 11:34:57 -07:00
starfive	riscv: dts: starfive: correct number of external interrupts	2022-08-11 11:40:37 -07:00
Makefile	RISC-V: Add BeagleV Starlight Beta device tree	2021-12-16 17:24:23 +01:00