Frieder Schrempf dd9e329af7 drm/bridge: ti-sn65dsi83: Fix enable/disable flow to meet spec ... The datasheet describes the following initialization flow including minimum delay times between each step: 1. DSI data lanes need to be in LP-11 and the clock lane in HS mode 2. toggle EN signal 3. initialize registers 4. enable PLL 5. soft reset 6. enable DSI stream 7. check error status register To meet this requirement we need to make sure the host bridge's pre_enable() is called first by using the pre_enable_prev_first flag. Furthermore we need to split enable() into pre_enable() which covers steps 2-5 from above and enable() which covers step 7 and is called after the host bridge's enable(). Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Fixes: ceb515ba29 ("drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 driver") Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> #TQMa8MxML/MBa8Mx Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230503163313.2640898-3-frieder@fris.de		2023-05-25 18:16:32 +02:00
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drm	drm/bridge: ti-sn65dsi83: Fix enable/disable flow to meet spec	2023-05-25 18:16:32 +02:00
host1x	drm/tegra: Changes for v6.4-rc1	2023-04-06 15:02:17 +02:00
ipu-v3	ipu-v3: Include <linux/io.h>	2023-05-18 11:06:18 +02:00
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