Tao Zhang dc6ce57e2a coresight-tpdm: Add timestamp control register support for the CMB ... CMB_TIER register is CMB subunit timestamp insertion enable register. Bit 0 is PATT_TSENAB bit. Set this bit to 1 to request a timestamp following a CMB interface pattern match. Bit 1 is XTRIG_TSENAB bit. Set this bit to 1 to request a timestamp following a CMB CTI timestamp request. Bit 2 is TS_ALL bit. Set this bit to 1 to request timestamp for all packets. Reviewed-by: James Clark <james.clark@arm.com> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com> Signed-off-by: Jinlong Mao <quic_jinlmao@quicinc.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/1707024641-22460-9-git-send-email-quic_taozha@quicinc.com		2024-02-12 10:29:47 +00:00
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coresight	coresight-tpdm: Add timestamp control register support for the CMB	2024-02-12 10:29:47 +00:00
intel_th	Driver core changes for 6.3-rc1	2023-02-24 12:58:55 -08:00
ptt	hwtracing: hisi_ptt: Optimize the trace data committing	2023-11-16 11:36:33 +00:00
stm	- Daniel Verkamp has contributed a memfd series ("mm/memfd: add	2023-02-23 17:09:35 -08:00
Kconfig	hwtracing: hisi_ptt: Add trace function support for HiSilicon PCIe Tune and Trace device	2022-09-08 16:26:17 -06:00